74HC273 Series

High Speed CMOS Logic Octal D-Type Flip-Flops with Reset

Catalog

High Speed CMOS Logic Octal D-Type Flip-Flops with Reset

Part	Current - Output High	Current - Output Low	Package Length	Package Name	Package Width	Number of Elements	Function	Max Propagation Delay	Max CL	Trigger Type	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Current - Quiescent (Iq)	Clock Frequency	Output Type	Type	Operating Temperature (Max)	Operating Temperature (Min)	Input Capacitance	Number of Bits per Element	Mounting Type
Texas Instruments SN74HC273PWRG4	5.2 mA	5.2 mA	0.173 in	20-TSSOP	4.4 mm	1	Master Reset	27 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	85 °C	-40 °C	3 pF	8 bits	Surface Mount
Texas Instruments SN74HC273PWT	5.2 mA	5.2 mA	0.173 in	20-TSSOP	4.4 mm	1	Master Reset	27 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	85 °C	-40 °C	3 pF	8 bits	Surface Mount
Texas Instruments SN74HC273DBRG4	5.2 mA	5.2 mA	0.209 in	20-SSOP	5.3 mm	1	Master Reset	27 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	85 °C	-40 °C	3 pF	8 bits	Surface Mount
Texas Instruments CD74HC273ME4	5.2 mA	5.2 mA	0.295 in	20-SOIC	7.5 mm	1	Master Reset	26 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	125 °C	-55 °C	10 pF	8 bits	Surface Mount
Texas Instruments SN74HC273DW	5.2 mA	5.2 mA	0.295 in	20-SOIC	7.5 mm	1	Master Reset	13 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	85 °C	-40 °C	3 pF	8 bits	Surface Mount
Texas Instruments SN74HC273NSR	5.2 mA	5.2 mA	0.209 in	20-SO 20-SOIC	5.3 mm	1	Master Reset	27 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	85 °C	-40 °C	3 pF	8 bits	Surface Mount
Texas Instruments SN74HC273DWRG4	5.2 mA	5.2 mA	0.295 in	20-SOIC	7.5 mm	1	Master Reset	27 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	85 °C	-40 °C	3 pF	8 bits	Surface Mount
Texas Instruments SN74HC273DWR	5.2 mA	5.2 mA	0.295 in	20-SOIC	7.5 mm	1	Master Reset	13 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	85 °C	-40 °C	3 pF	8 bits	Surface Mount
Texas Instruments CD74HC273E	5.2 mA	5.2 mA	0.3 in	20-DIP 20-PDIP	7.62 mm	1	Master Reset	26 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	125 °C	-55 °C	10 pF	8 bits	Through Hole
Texas Instruments SN74HC273QPWRG4Q1	5.2 mA	5.2 mA	0.173 in	20-TSSOP	4.4 mm	1	Master Reset	27 ns	50 pF	Positive Edge	2 V	6 V	8 µA	60 MHz	Non-Inverted	D-Type	125 °C	-40 °C	3 pF	8 bits	Surface Mount

Catalog

High Speed CMOS Logic Octal D-Type Flip-Flops with Reset

Description

This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.