DAC5675A-SP Series
QMLV, 150-krad, ceramic, 14-bit, single-channel, 400-MSPS DAC
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
QMLV, 150-krad, ceramic, 14-bit, single-channel, 400-MSPS DAC
| Part | Supplier Device Package | Differential Output | Voltage - Supply, Digital [Max] | Voltage - Supply, Digital [Min] | Architecture | Settling Time | Mounting Type | Data Interface | Number of Bits | Reference Type | Voltage - Supply, Analog [Min] | Voltage - Supply, Analog [Max] | Operating Temperature [Min] | Operating Temperature [Max] | INL/DNL (LSB) [Max] | INL/DNL (LSB) [Min] | Output Type | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments DAC5675AHFG/EM | 52-CFP | 3.6 V | 3.15 V | Current Source | 12 ns | Surface Mount | LVDS - Parallel | 14 | External, Internal | 3.15 V | 3.6 V | -40 °C | 85 °C | 1.5 LSB | -1.5 LSB | Current - Unbuffered | 52-CFlatPack |
Key Features
• QMLV (QML Class V) MIL-PRF-38535 Qualified, SMD 5962-072045962-0720401VXC – Qualified over the Military Temperature Range (–55°C to 125°C)5962-0720402VXC – Qualified over Reduced Temperature Range (–55°C to 115°C) for Improved Dynamic PerformanceHigh-Performance 52-Pin Ceramic Quad Flat Pack (HFG)400-MSPS Update RateLVDS-Compatible Input InterfaceSpurious-Free Dynamic Range (SFDR) to Nyquist69 dBc at 70 MHz IF, 400 MSPSW-CDMA Adjacent Channel Power Ratio (ACPR)73 dBc at 30.72 MHz IF, 122.88 MSPS71 dBc at 61.44 MHz IF, 245.76 MSPSDifferential Scalable Current Outputs: 2 to 20 mAOn-Chip 1.2-V ReferenceSingle 3.3-V Supply OperationPower Dissipation: 660 mW at ƒCLK= 400 MSPS, ƒOUT= 20 MHzAPPLICATIONSRadiation Hardened Digital to Analog (DAC) ApplicationsSpace Satellite RF Data TransmissionCellular Base Transceiver Station Transmit Channel:CDMA: WCDMA, CDMA2000, IS-95TDMA: GSM, IS-136, EDGE/GPRSSupports Single-Carrier and Multicarrier ApplicationsEngineering Evaluation (/EM) Samples are Available(1)(1)These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.All other trademarks are the property of their respective ownersQMLV (QML Class V) MIL-PRF-38535 Qualified, SMD 5962-072045962-0720401VXC – Qualified over the Military Temperature Range (–55°C to 125°C)5962-0720402VXC – Qualified over Reduced Temperature Range (–55°C to 115°C) for Improved Dynamic PerformanceHigh-Performance 52-Pin Ceramic Quad Flat Pack (HFG)400-MSPS Update RateLVDS-Compatible Input InterfaceSpurious-Free Dynamic Range (SFDR) to Nyquist69 dBc at 70 MHz IF, 400 MSPSW-CDMA Adjacent Channel Power Ratio (ACPR)73 dBc at 30.72 MHz IF, 122.88 MSPS71 dBc at 61.44 MHz IF, 245.76 MSPSDifferential Scalable Current Outputs: 2 to 20 mAOn-Chip 1.2-V ReferenceSingle 3.3-V Supply OperationPower Dissipation: 660 mW at ƒCLK= 400 MSPS, ƒOUT= 20 MHzAPPLICATIONSRadiation Hardened Digital to Analog (DAC) ApplicationsSpace Satellite RF Data TransmissionCellular Base Transceiver Station Transmit Channel:CDMA: WCDMA, CDMA2000, IS-95TDMA: GSM, IS-136, EDGE/GPRSSupports Single-Carrier and Multicarrier ApplicationsEngineering Evaluation (/EM) Samples are Available(1)(1)These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.All other trademarks are the property of their respective owners
Description
AI
The DAC5675A-SP is a radiation-tolerant, 14-bit resolution high-speed digital-to-analog converter (DAC) primarily suited for space satellite applications. The DAC5675A-SP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A-SP has excellent SFDR at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).
The DAC5675A-SP operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at ƒCLK= 400 MSPS, ƒOUT= 70 MHz. The DAC5675A-SP provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.
The DAC5675A-SP includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels (low electromagnetic interference (EMI)).
LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A-SP and high-speed low-voltage CMOS ASICs or FPGAs.
The DAC5675A-SP current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.
The DAC5675A-SP is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD– 1 to AVDD+ 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A-SP features a SLEEP mode, which reduces the standby power to approximately 18 mW.
The DAC5675A-SP is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of –55°C to 125°C and W temperature range of –55°C to 115°C.
The DAC5675A-SP is a radiation-tolerant, 14-bit resolution high-speed digital-to-analog converter (DAC) primarily suited for space satellite applications. The DAC5675A-SP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A-SP has excellent SFDR at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).
The DAC5675A-SP operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at ƒCLK= 400 MSPS, ƒOUT= 70 MHz. The DAC5675A-SP provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.
The DAC5675A-SP includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels (low electromagnetic interference (EMI)).
LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A-SP and high-speed low-voltage CMOS ASICs or FPGAs.
The DAC5675A-SP current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.
The DAC5675A-SP is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD– 1 to AVDD+ 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A-SP features a SLEEP mode, which reduces the standby power to approximately 18 mW.
The DAC5675A-SP is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of –55°C to 125°C and W temperature range of –55°C to 115°C.