ADC34J43 Series
Quad-Channel, 14-Bit, 80-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Quad-Channel, 14-Bit, 80-MSPS Analog-to-Digital Converter (ADC)
| Part | Configuration | Voltage - Supply, Analog [Min] | Voltage - Supply, Analog [Max] | Supplier Device Package | Number of Bits | Data Interface | Mounting Type | Reference Type | Number of Inputs | Architecture | Number of A/D Converters | Sampling Rate (Per Second) | Operating Temperature [Min] | Operating Temperature [Max] | Features | Input Type | Voltage - Supply, Digital [Min] | Voltage - Supply, Digital [Max] | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC34J43IRGZT | ADC | 1.7 V | 1.9 V | 48-VQFN (7x7) | 14 | JESD204B | Surface Mount | External, Internal | 4 | Pipelined | 4 | 80 M | -40 °C | 85 °C | Simultaneous Sampling | Differential | 1.7 V | 1.9 V | 48-VFQFN Exposed Pad |
Texas Instruments ADC34J43IRGZR | ADC | 1.7 V | 1.9 V | 48-VQFN (7x7) | 14 | JESD204B | Surface Mount | External, Internal | 4 | Pipelined | 4 | 80 M | -40 °C | 85 °C | Simultaneous Sampling | Differential | 1.7 V | 1.9 V | 48-VFQFN Exposed Pad |
Key Features
• Quad Channel14-Bit ResolutionSingle 1.8-V SupplyFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 72 dBFS, SFDR = 86 dBc atfIN= 70 MHzUltra-Low Power Consumption:203 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Supports Subclass 0, 1, 2Supports One Lane per ADC up to 160 MSPSSupport for Multi-Chip SynchronizationPin-to-Pin Compatible with 12-Bit VersionPackage: VQFN-48 (7 mm × 7 mm)Quad Channel14-Bit ResolutionSingle 1.8-V SupplyFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 72 dBFS, SFDR = 86 dBc atfIN= 70 MHzUltra-Low Power Consumption:203 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Supports Subclass 0, 1, 2Supports One Lane per ADC up to 160 MSPSSupport for Multi-Chip SynchronizationPin-to-Pin Compatible with 12-Bit VersionPackage: VQFN-48 (7 mm × 7 mm)
Description
AI
The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.
The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.