SPC56B-Discovery Series
32-bit Power Architecture MCU for Automotive Chassis and Safety Applications
Manufacturer: STMicroelectronics
Catalog
32-bit Power Architecture MCU for Automotive Chassis and Safety Applications
Key Features
• Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h)
- Compliant with Power Architecture®embedded category
- Variable Length Encoding (VLE)
• Memory organization
- Up to 256 KB on-chip code flash memory with ECC and erase/program controller
- Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation
- Up to 20 KB on-chip SRAM with ECC
• Fail-safe protection
- Programmable watchdog timer
- Non-maskable interrupt
- Fault collection unit
• Interrupts and events
- 16-channel eDMA controller
- 16 priority level controller
- Up to 25 external interrupts
- PIT implements four 32-bit timers
- 120 interrupts are routed via INTC
• 1 general purpose eTimer unit
- 6 timers each with up/down capabilities
- 16-bit resolution, cascadable counters
- Quadrature decode with rotation direction flag
- Double buffer input capture and output compare
Description
AI
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit) and provides improved code density. It operates at speed of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations.
The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory.