ADC3244 Series
Dual-channel 14-bit 125-MSPS analog-to-digital converter (ADC) with extended temperature range
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Operating Temperature▲▼ | Operating Temperature▲▼ | Reference Type | Number of A/D Converters▲▼ | Sampling Rate (Per Second)▲▼ | Package / Case | Input Type | Ratio - S/H:ADC | Mounting Type | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Number of Bits▲▼ | Configuration | Architecture | Number of Inputs▲▼ | Supplier Device Package | Data Interface |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
105 °C | -50 °C | External, Internal | 2 ul | 125 m | 48-VFQFN Exposed Pad | Differential | 0:1 | Surface Mount | 1.7000000476837158 V | 1.899999976158142 V | 1.7000000476837158 V | 1.899999976158142 V | 14 ul | ADC | Pipelined | 2 ul | 48-VQFN (7x7) | LVDS - Serial |
Key Features
• Dual channel14-bit resolutionSingle supply: 1.8 VSerial LVDS interface (SLVDS)Flexible input clock buffer with divide-by-1, -2, -4SNR = 72.4 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltra-low power consumption:116 mW/Ch at 125 MSPSChannel isolation: 105 dBInternal dither and chopperSupport for multichip synchronizationPin-to-pin compatible with 12-bit versionPackage: VQFN-48 (7 mm × 7 mm)Extended temperature range: –50°C to +105°CDual channel14-bit resolutionSingle supply: 1.8 VSerial LVDS interface (SLVDS)Flexible input clock buffer with divide-by-1, -2, -4SNR = 72.4 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltra-low power consumption:116 mW/Ch at 125 MSPSChannel isolation: 105 dBInternal dither and chopperSupport for multichip synchronizationPin-to-pin compatible with 12-bit versionPackage: VQFN-48 (7 mm × 7 mm)Extended temperature range: –50°C to +105°C
Description
AI
The ADC3244E is a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization.
The ADC3244E supports serial, low-voltage, differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where the data from each ADC are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The ADC3244E is a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization.
The ADC3244E supports serial, low-voltage, differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where the data from each ADC are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.