CDCE906 Series
167-MHz, LVCMOS, programmable 3-PLL clock synthesizer / multiplier / divider
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
167-MHz, LVCMOS, programmable 3-PLL clock synthesizer / multiplier / divider
| Part | Input | Operating Temperature [Max] | Operating Temperature [Min] | Differential - Input:Output | Package / Case | Package / Case | Package / Case | Number of Circuits | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | PLL | Output | Voltage - Supply [Max] | Voltage - Supply [Min] | Mounting Type | Supplier Device Package | Frequency - Max [Max] | For Use With/Related Products | Type | Contents | Function | Supplied Contents | Utilized IC / Part |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCE906PWR | Crystal, LVCMOS | 70 ░C | 0 °C | Yes/No | 0.173 in | 4.4 mm | 20-TSSOP | 1 | 6 | 1 | Yes with Bypass | LVCMOS | 3.6 V | 3 V | Surface Mount | 20-TSSOP | 167 MHz | ||||||
Texas Instruments CDCE906-706PROGEVM | CDCE706, CDCE906 | Programmer | Board(s) | ||||||||||||||||||||
Texas Instruments CDCE906-706PERFEVM | Timing | Clock Generator | Board(s) | CDCE706, CDCE906 |
Key Features
• High Performance 3:6 PLL based Clock Synthesizer / Multiplier / DividerUser Programmable PLL FrequenciesEEPROM Programming Without the Need to Apply High Programming VoltageEasy In-Circuit Programming via SMBus Data InterfaceWide PLL Divider Ratio Allows 0-ppm Output Clock ErrorGenerates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS= 16, 22.05, 24, 32, 44.1, 48, 96 kHz)Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input SignalAccepts Crystal Frequencies from 8 MHz up to 54 MHzAccepts LVCMOS or Differential Input Frequencies up to 167 MHzTwo Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control SignalsSix LVCMOS Outputs with Output Frequencies up to 167 MHzLVCMOS Outputs can be Programmed for Complementary SignalsFree Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each OutputPLL Loop Filter Components IntegratedLow Period Jitter (Typ 60 ps)Features Spread Spectrum Clocking (SSC) for Lowering System EMIProgrammable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated FrequencyProgrammable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)Programmable Output Slew-Rate Control (SRC) for Lowering System EMI3.3-V Device Power SupplyCommercial Temperature Range 0°C to 70°CDevelopment and Programming Kit for Easy PLL Design and Programming(TI Pro-Clock™)Packaged in 20-Pin TSSOPPro-Clock is a trademark of Texas Instruments.High Performance 3:6 PLL based Clock Synthesizer / Multiplier / DividerUser Programmable PLL FrequenciesEEPROM Programming Without the Need to Apply High Programming VoltageEasy In-Circuit Programming via SMBus Data InterfaceWide PLL Divider Ratio Allows 0-ppm Output Clock ErrorGenerates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS= 16, 22.05, 24, 32, 44.1, 48, 96 kHz)Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input SignalAccepts Crystal Frequencies from 8 MHz up to 54 MHzAccepts LVCMOS or Differential Input Frequencies up to 167 MHzTwo Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control SignalsSix LVCMOS Outputs with Output Frequencies up to 167 MHzLVCMOS Outputs can be Programmed for Complementary SignalsFree Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each OutputPLL Loop Filter Components IntegratedLow Period Jitter (Typ 60 ps)Features Spread Spectrum Clocking (SSC) for Lowering System EMIProgrammable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated FrequencyProgrammable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)Programmable Output Slew-Rate Control (SRC) for Lowering System EMI3.3-V Device Power SupplyCommercial Temperature Range 0°C to 70°CDevelopment and Programming Kit for Easy PLL Design and Programming(TI Pro-Clock™)Packaged in 20-Pin TSSOPPro-Clock is a trademark of Texas Instruments.
Description
AI
The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.
The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.
To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.
The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).
The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.
PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.
Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.
The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.
Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).
The CDCE906 has three power supply pins, VCC, VCCOUT1and VCCOUT2. VCCis the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1and VCCOUT2are the power supply pins for the outputs. VCCOUT1supplies the outputs Y0 and Y1 and VCCOUT2supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.
The CDCE906 is characterized for operation from 0°C to 70°C.
The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.
The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.
To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.
The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).
The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.
PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.
Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.
The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.
Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).
The CDCE906 has three power supply pins, VCC, VCCOUT1and VCCOUT2. VCCis the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1and VCCOUT2are the power supply pins for the outputs. VCCOUT1supplies the outputs Y0 and Y1 and VCCOUT2supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.
The CDCE906 is characterized for operation from 0°C to 70°C.