CLVTH16543 Series
Enhanced Product 3.3-V Abt 16-Bit Registered Transceiver With 3-State Outputs
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Enhanced Product 3.3-V Abt 16-Bit Registered Transceiver With 3-State Outputs
| Part | Supplier Device Package | Mounting Type | Package / Case | Package / Case | Package / Case | Output Type | Number of Bits per Element | Voltage - Supply [Min] | Voltage - Supply [Max] | Number of Elements [custom] | Operating Temperature [Max] | Operating Temperature [Min] | Current - Output High, Low | Package / Case [x] | Package / Case [x] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CLVTH16543IDGGREP | 56-TSSOP | Surface Mount | 56-TFSOP | 6.1 mm | 0.24 " | 3-State | 8 | 2.7 V | 3.6 V | 2 | 85 °C | -40 °C | 32 mA, 64 mA | ||
Texas Instruments CLVTH16543MDLREP | 56-SSOP | Surface Mount | 56-BSSOP | 3-State | 8 | 2.7 V | 3.6 V | 2 | 125 °C | -55 C | 32 mA, 64 mA | 0.295 in | 7.5 mm |
Key Features
• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product–Change NotificationQualification Pedigree(1)Member of the Texas Instruments Widebus™ FamilyState–of–the–Art Advanced BiCMOS Technology (ABT) Design for 3.3–V Operation and Low Static–Power DissipationSupports Mixed–Mode Signal Operation (5–V Input and Output Voltages With 3.3–V VCC)Supports Unregulated Battery Operation Down to 2.7 VIoffand Power–Up 3–State Support Hot InsertionBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CDistributed VCCand GND Pins Minimize High–Speed Switching NoiseFlow–Through Architecture Optimizes PCB LayoutLatch–Up Performance Exceeds 500 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL–STD–883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Widebus Is a trademark of Texas InstrumentsControlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product–Change NotificationQualification Pedigree(1)Member of the Texas Instruments Widebus™ FamilyState–of–the–Art Advanced BiCMOS Technology (ABT) Design for 3.3–V Operation and Low Static–Power DissipationSupports Mixed–Mode Signal Operation (5–V Input and Output Voltages With 3.3–V VCC)Supports Unregulated Battery Operation Down to 2.7 VIoffand Power–Up 3–State Support Hot InsertionBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CDistributed VCCand GND Pins Minimize High–Speed Switching NoiseFlow–Through Architecture Optimizes PCB LayoutLatch–Up Performance Exceeds 500 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL–STD–883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Widebus Is a trademark of Texas Instruments
Description
AI
The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCCoperation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEABorLEBA) and output–enable (OEABorOEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. IfCEABis low andLEABis low, the A–to–B latches are transparent; a subsequent low–to–high transition ofLEABputs the A latches in the storage mode. WithCEABandOEABboth low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using theCEBA,LEBA, andOEBAinputs.
Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver.
This device is fully specified for hot–insertion applications using Ioffand power–up 3–state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict.
The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCCoperation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEABorLEBA) and output–enable (OEABorOEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. IfCEABis low andLEABis low, the A–to–B latches are transparent; a subsequent low–to–high transition ofLEABputs the A latches in the storage mode. WithCEABandOEABboth low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using theCEBA,LEBA, andOEBAinputs.
Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver.
This device is fully specified for hot–insertion applications using Ioffand power–up 3–state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict.