CDCLVP1216 Series
Low jitter, 2-input selectable 1:16 universal-to-LVPECL buffer
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Low jitter, 2-input selectable 1:16 universal-to-LVPECL buffer
| Part | Input | Voltage - Supply [Min] | Voltage - Supply [Max] | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Mounting Type | Package / Case | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Number of Circuits | Frequency - Max [Max] | Supplier Device Package | Output | Type | Operating Temperature [Min] | Operating Temperature [Max] | Function | Embedded | Supplied Contents | Utilized IC / Part |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVP1216RGZR | LVCMOS, LVDS, LVPECL, LVTTL | 2.375 V | 3.6 V | 16 | 2 | Surface Mount | 48-VFQFN Exposed Pad | 1 | 2 GHz | 48-VQFN (7x7) | LVPECL | Fanout Buffer (Distribution), Multiplexer | -40 °C | 85 °C | ||||||
Texas Instruments CDCLVP1216RGZT | LVCMOS, LVDS, LVPECL, LVTTL | 2.375 V | 3.6 V | 16 | 2 | Surface Mount | 48-VFQFN Exposed Pad | 1 | 2 GHz | 48-VQFN (7x7) | LVPECL | Fanout Buffer (Distribution), Multiplexer | -40 °C | 85 °C | ||||||
Texas Instruments CDCLVP1216EVM | Timing | Clock Buffer | Board(s) | CDCLVP1216 |
Key Features
• 2:16 Differential BufferSelectable Clock Inputs Through Control PinUniversal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL16 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 110 mAVery Low Additive Jitter: <100 fs, RMS in 10-kHz to20-MHz Offset Range:57 fs, RMS (Typical) at 122.88 MHz48 fs, RMS (Typical) at 156.25 MHz30 fs, RMS (Typical) at 312.5 MHz2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Output Skew: 30 psLVPECL Reference Voltage, VAC_REF, Availablefor Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to +85°CSupports 105°C PCB Temperature (Measured with aThermal Pad)ESD Protection Exceeds 2000 V (HBM)Available in 7-mm × 7-mm VQFN-48 (RGZ) Package2:16 Differential BufferSelectable Clock Inputs Through Control PinUniversal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL16 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 110 mAVery Low Additive Jitter: <100 fs, RMS in 10-kHz to20-MHz Offset Range:57 fs, RMS (Typical) at 122.88 MHz48 fs, RMS (Typical) at 156.25 MHz30 fs, RMS (Typical) at 312.5 MHz2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Output Skew: 30 psLVPECL Reference Voltage, VAC_REF, Availablefor Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to +85°CSupports 105°C PCB Temperature (Measured with aThermal Pad)ESD Protection Exceeds 2000 V (HBM)Available in 7-mm × 7-mm VQFN-48 (RGZ) Package
Description
AI
The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1216 is packaged in a small 48-pin, 7-mm × 7-mm VQFN package and is characterized for operation from –40°C to +85°C.
The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1216 is packaged in a small 48-pin, 7-mm × 7-mm VQFN package and is characterized for operation from –40°C to +85°C.