ADC12DL3200 Series
12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (LVDS interface)
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Package / Case | Configuration | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Number of Inputs▲▼ | Data Interface | Number of A/D Converters▲▼ | Mounting Type | Input Type | Ratio - S/H:ADC | Reference Type | Sampling Rate (Per Second)▲▼ | Supplier Device Package | Features | Operating Temperature▲▼ | Operating Temperature▲▼ | Architecture | Number of Bits▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC12DL3200ACF12 Bit Analog to Digital Converter 1, 2 Input 2 Folding Interpolating 256-FCBGA (17x17) | 1.0499999523162842 V | 2 V | 256-BBGA, FCBGA | MUX-ADC | 1.0499999523162842 V | 2 V | 1 ul, 2 ul | LVDS - Parallel | 2 ul | Surface Mount | Differential, Single Ended | 0:1 | Internal | 3200000000 Ω, 6400000000 Ω | 256-FCBGA (17x17) | Simultaneous Sampling | -40 °C | 85 °C | Folding Interpolating | 12 ul |
Key Features
• ADC Core:12-Bit ResolutionUp to 6.4 GSPS in Single-Channel ModeUp to 3.2 GSPS in Dual-Channel ModeInternal Dither for Low-Magnitude, High-Order HarmonicsLow-Latency LVDS Interface:Total Latency: < 10 nsUp to 48 Data Pairs at 1.6 GbpsFour DDR Data ClocksStrobe Signals Simplify SynchronizationNoise Floor (No Input, V FS = 1.0 V PP-DIFF):Dual-Channel Mode: –151.1 dBFS/HzSingle-Channel Mode: –154.3 dBFS/HzBuffered Analog Inputs With V CMI of 0 V:Analog Input Bandwidth (–3 dB): 8.0 GHzUsable Input Frequency Range: > 10 GHzFull-Scale Input Voltage (V FS, Default): 0.8 V PPNoiseless Aperture Delay (T AD) Adjustment:Precise Sampling Control: 19-fs StepSimplifies Synchronization and InterleavingTemperature and Voltage Invariant DelaysEasy-to-Use Synchronization Features:Automatic SYSREF Timing CalibrationTimestamp for Sample MarkingPower Consumption: 3.15 WADC Core:12-Bit ResolutionUp to 6.4 GSPS in Single-Channel ModeUp to 3.2 GSPS in Dual-Channel ModeInternal Dither for Low-Magnitude, High-Order HarmonicsLow-Latency LVDS Interface:Total Latency: < 10 nsUp to 48 Data Pairs at 1.6 GbpsFour DDR Data ClocksStrobe Signals Simplify SynchronizationNoise Floor (No Input, V FS = 1.0 V PP-DIFF):Dual-Channel Mode: –151.1 dBFS/HzSingle-Channel Mode: –154.3 dBFS/HzBuffered Analog Inputs With V CMI of 0 V:Analog Input Bandwidth (–3 dB): 8.0 GHzUsable Input Frequency Range: > 10 GHzFull-Scale Input Voltage (V FS, Default): 0.8 V PPNoiseless Aperture Delay (T AD) Adjustment:Precise Sampling Control: 19-fs StepSimplifies Synchronization and InterleavingTemperature and Voltage Invariant DelaysEasy-to-Use Synchronization Features:Automatic SYSREF Timing CalibrationTimestamp for Sample MarkingPower Consumption: 3.15 W
Description
AI
The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.
The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.