CDCVF2505-Q1 Series

Automotive PLL clock driver for synchronization, DRAM & gen-purpose apps with spread-spectrum compat

Link to Manufacturer Page: https://www.ti.com/

Catalog

Automotive PLL clock driver for synchronization, DRAM & gen-purpose apps with spread-spectrum compat

Part	Operating Temperature [Min]	Operating Temperature [Max]	PLL	Grade	Frequency - Max [Max]	Package / Case	Package / Case	Supplier Device Package	Ratio - Input:Output [custom]	Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Divider/Multiplier [custom]	Divider/Multiplier [custom]	Number of Circuits	Output	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Qualification	Mounting Type
Texas Instruments CDCVF2505IDRQ1	-40 °C	85 °C	Yes with Bypass	Automotive	200 MHz	3.9 mm	8-SOIC	8-SOIC	1:5	PLL Clock Driver	3.6 V	3 V			1	LVTTL			AEC-Q100	Surface Mount

Key Features

• Qualified for Automotive ApplicationsPhase-Locked Loop Clock Driver for Synchronous DRAMand General-Purpose ApplicationsSpread-Spectrum Clock CompatibleOperating Frequency: 24 MHz to 200 MHzLow Jitter (Cycle-to-Cycle): <150 ps Over theRange 66 MHz to 200 MHzDistributes One Clock Input to One Bank of Five Outputs(CLKOUT Is Used to Tune the Input-Output Delay)Three-States Outputs When There Is No Input ClockOperates From Single 3.3-V SupplyAvailable in 8-Pin SOIC PackageConsumes Less Than 100 µA (Typically) inPower Down ModeInternal Feedback Loop Is Used to Synchronize theOutputs to the Input Clock25-On-Chip Series Damping ResistorsIntegrated RC PLL Loop Filter Eliminates theNeed for External ComponentsQualified for Automotive ApplicationsPhase-Locked Loop Clock Driver for Synchronous DRAMand General-Purpose ApplicationsSpread-Spectrum Clock CompatibleOperating Frequency: 24 MHz to 200 MHzLow Jitter (Cycle-to-Cycle): <150 ps Over theRange 66 MHz to 200 MHzDistributes One Clock Input to One Bank of Five Outputs(CLKOUT Is Used to Tune the Input-Output Delay)Three-States Outputs When There Is No Input ClockOperates From Single 3.3-V SupplyAvailable in 8-Pin SOIC PackageConsumes Less Than 100 µA (Typically) inPower Down ModeInternal Feedback Loop Is Used to Synchronize theOutputs to the Input Clock25-On-Chip Series Damping ResistorsIntegrated RC PLL Loop Filter Eliminates theNeed for External Components

Description

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN. Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost. Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference. The CDCVF2505 is characterized for operation from –40°C to 85°C. The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN. Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost. Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference. The CDCVF2505 is characterized for operation from –40°C to 85°C.