8101602 Series
CMOS Presettable Up/Down Counter
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
CMOS Presettable Up/Down Counter
| Part | Supplier Device Package | Trigger Type | Direction | Mounting Type | Logic Type | Number of Bits per Element | Number of Elements [custom] | Operating Temperature [Min] | Operating Temperature [Max] | Voltage - Supply [Max] | Voltage - Supply [Min] | Reset | Count Rate | Package / Case | Timing |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments 8101602EA | 16-CDIP | Positive Edge | Down, Up | Through Hole | Binary Counter, Decade | 4 | 1 | -55 C | 125 °C | 18 V | 3 V | Asynchronous | 11 MHz | 16-CDIP (0.300", 7.62mm) | Synchronous |
Key Features
• Medium-speed operation… 8 MHz (typ.) @ CL= 50 pF and VDD–VSS= 10 VMulti-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times"Preset Enable" and individual "Jam" inputs providedBinary or decade up/down countingBCD outputs in decade mode100% tested for quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsStandardized, symmetrical output characteristicsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Applications:Programmable binary and decade counting/frequency synthesizers-BCD outputAnalog to digital and digital to analog conversionUp/Down binary countingMagnitude and sign generationUp/Down decade countingDifference countingMedium-speed operation… 8 MHz (typ.) @ CL= 50 pF and VDD–VSS= 10 VMulti-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times"Preset Enable" and individual "Jam" inputs providedBinary or decade up/down countingBCD outputs in decade mode100% tested for quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsStandardized, symmetrical output characteristicsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Applications:Programmable binary and decade counting/frequency synthesizers-BCD outputAnalog to digital and digital to analog conversionUp/Down binary countingMagnitude and sign generationUp/Down decade countingDifference counting
Description
AI
CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low. The CARRY-IN\ signal in the low state can thus be considered a CLOCK ENABLE\. The CARRY-IN\ terminal must be connected to VSSwhen not in use.
Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement as shown in Fig. 17.
Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.
The CD4029B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low. The CARRY-IN\ signal in the low state can thus be considered a CLOCK ENABLE\. The CARRY-IN\ terminal must be connected to VSSwhen not in use.
Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement as shown in Fig. 17.
Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.
The CD4029B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).