74LV10 Series

3-ch, 3-input, 2-V to 5.5-V NAND gates

Catalog

3-ch, 3-input, 2-V to 5.5-V NAND gates

Part	Number of Inputs	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Package Name	Input Logic Level - High	Current - Quiescent (Max)	Number of Circuits	Max Propagation Delay	Max CL	Mounting Type	Logic Type	Current - Output High	Current - Output Low	Input Logic Level - Low (Voltage)	Operating Temperature (Min)	Operating Temperature (Max)	Package Width	Package Length
Texas Instruments SN74LV10APWRG4	3	5.5 V	2 V	14-TSSOP	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	4.4 mm	0.173 in
Texas Instruments SN74LV10ADBR	3	5.5 V	2 V	14-SSOP	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	5.3 mm	0.209 in
Texas Instruments SN74LV10ADRG4	3	5.5 V	2 V	14-SOIC	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	3.9 mm	0.154 in
Texas Instruments SN74LV10ANSR	3	5.5 V	2 V	14-SO 14-SOIC	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	5.3 mm	0.209 in
Texas Instruments SN74LV10AD	3	5.5 V	2 V	14-SOIC	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	3.9 mm	0.154 in
Texas Instruments SN74LV10ADGVRE4	3	5.5 V	2 V	14-TFSOP 14-TVSOP	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	4.4 mm	0.173 in
Texas Instruments SN74LV10APWR	3	5.5 V	2 V	14-TSSOP	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	4.4 mm	0.173 in
Texas Instruments SN74LV10ADR	3	5.5 V	2 V	14-SOIC	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	3.9 mm	0.154 in
Texas Instruments SN74LV10APWT	3	5.5 V	2 V	14-TSSOP	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	4.4 mm	0.173 in
Texas Instruments SN74LV10APW	3	5.5 V	2 V	14-TSSOP	1.5 V	20 µA	3	7.9 ns	50 pF	Surface Mount	NAND Gate	12 mA	12 mA	0.5 V	-40 °C	85 °C	4.4 mm	0.173 in

Catalog

3-ch, 3-input, 2-V to 5.5-V NAND gates

Description

These triple 3-input positive-NAND gates are designed for 2 V to 5.5 V VCCoperation. The SN74LV10A devices perform the Boolean function Y =A • B • Cin positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. These triple 3-input positive-NAND gates are designed for 2 V to 5.5 V VCCoperation. The SN74LV10A devices perform the Boolean function Y =A • B • Cin positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.