ADC3444 Series

Quad-Channel, 14-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

Link to Manufacturer Page: https://www.ti.com/

Catalog

Quad-Channel, 14-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

Part	Input Type	Sampling Rate (Per Second)	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Supplier Device Package	Data Interface	Features	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Operating Temperature [Min]	Operating Temperature [Max]	Architecture	Number of A/D Converters	Number of Bits	Configuration	Number of Inputs	Package / Case	Reference Type	Mounting Type	Input Range	Power (Typ) @ Conditions	Utilized IC / Part	Supplied Contents	Ratio - S/H:ADC
Texas Instruments ADC3444IRTQT	Differential	125 M	1.7 V	1.9 V	56-QFN (8x8)	LVDS - Serial	Simultaneous Sampling	1.7 V	1.9 V	-40 °C	85 °C	Pipelined	4	14	ADC	4	56-VFQFN Exposed Pad	External, Internal	Surface Mount
Texas Instruments ADC3444EVM		125 M				LVDS - Serial							4	14						2 Vpp	391 mW	ADC3444	Board(s)
Texas Instruments ADC3444IRTQR	Differential	125 M	1.7 V	1.9 V	56-QFN (8x8)	LVDS - Serial		1.7 V	1.9 V	-40 °C	85 °C	Pipelined	4	14	ADC	4	56-VFQFN Exposed Pad	External, Internal	Surface Mount					0:1

Key Features

• Quad Channel14-Bit ResolutionSingle Supply: 1.8 VSerial LVDS InterfaceFlexible Input Clock Buffer With Divide-by-1, -2, -4SNR = 72.4 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltra-Low Power Consumption:98 mW/Ch at 125 MSPSChannel Isolation: 105 dBInternal Dither and ChopperSupport for Multi-Chip SynchronizationPin-to-Pin Compatible With 12-Bit VersionPackage: VQFN-56 (8 mm × 8 mm)Quad Channel14-Bit ResolutionSingle Supply: 1.8 VSerial LVDS InterfaceFlexible Input Clock Buffer With Divide-by-1, -2, -4SNR = 72.4 dBFS, SFDR = 87 dBc atfIN= 70 MHzUltra-Low Power Consumption:98 mW/Ch at 125 MSPSChannel Isolation: 105 dBInternal Dither and ChopperSupport for Multi-Chip SynchronizationPin-to-Pin Compatible With 12-Bit VersionPackage: VQFN-56 (8 mm × 8 mm)

Description

The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs. The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs.