CDCLVD2104 Series
Low jitter, dual 1:4 universal-to-LVDS buffer
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Low jitter, dual 1:4 universal-to-LVDS buffer
| Part | Mounting Type | Supplier Device Package | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Type | Output | Input | Frequency - Max [Max] | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Number of Circuits | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Voltage - Supply [Min] | Voltage - Supply [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVD2104RHDT | Surface Mount | 28-VQFN (5x5) | 28-VFQFN Exposed Pad | -40 °C | 85 °C | Fanout Buffer (Distribution) | LVDS | LVCMOS, LVDS, LVPECL | 800 MHz | 4 | 1 | 2 | 2.375 V | 2.625 V | ||
Texas Instruments CDCLVD2104RHDR | Surface Mount | 28-VQFN (5x5) | 28-VFQFN Exposed Pad | -40 °C | 85 °C | Fanout Buffer (Distribution) | LVDS | LVCMOS, LVDS, LVPECL | 800 MHz | 4 | 1 | 2 | 2.375 V | 2.625 V |
Key Features
• Dual 1:4 Differential BufferLow Additive Jitter <300 fs, RMS in10 kHz to 20 MHzLow Within Bank Output Skew of 35ps (Max)Universal Inputs Accept LVDS, LVPECL, LVCMOSOne Input Dedicated for Four Output Buffers8 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency up to 800 MHz2.375–2.625V Device Power SupplyLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range –40°C to 85°CPackaged in 5mm × 5mm 28-Pin QFN (RHD)ESD Protection Exceeds 3 kV HBM, 1 kV CDMAPPLICATIONSTelecommunications/NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose ClockingDual 1:4 Differential BufferLow Additive Jitter <300 fs, RMS in10 kHz to 20 MHzLow Within Bank Output Skew of 35ps (Max)Universal Inputs Accept LVDS, LVPECL, LVCMOSOne Input Dedicated for Four Output Buffers8 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency up to 800 MHz2.375–2.625V Device Power SupplyLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range –40°C to 85°CPackaged in 5mm × 5mm 28-Pin QFN (RHD)ESD Protection Exceeds 3 kV HBM, 1 kV CDMAPPLICATIONSTelecommunications/NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose Clocking
Description
AI
The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2104 is specifically designed for driving 50-transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2104 is packaged in small 28-pin, 5-mm × 5-mm QFN package.
The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2104 is specifically designed for driving 50-transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2104 is packaged in small 28-pin, 5-mm × 5-mm QFN package.