CDCE925 Series

Programmable 2-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs

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Catalog

Programmable 2-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs

Part	Utilized IC / Part	Supplied Contents	Function	Type	Package / Case [x]	Package / Case	Package / Case [x]	Ratio - Input:Output [custom]	Output	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Number of Circuits	Operating Temperature [Min]	Operating Temperature [Max]	Frequency - Max [Max]	PLL	Input	Divider/Multiplier	Supplier Device Package
Texas Instruments CDCE925PERF-EVM	CDCE925PERF	Board(s)	Clock Generator	Timing
Texas Instruments CDCE925PW				PLL Clock Generator	0.173 "	16-TSSOP	4.4 mm	1:5	LVCMOS	1.7 V	1.9 V	Surface Mount	1	-40 °C	85 °C	230 MHz	Yes with Bypass	Crystal, LVCMOS	Yes/No	16-TSSOP
Texas Instruments CDCE925PWRG4				PLL Clock Generator	0.173 "	16-TSSOP	4.4 mm	1:5	LVCMOS	1.7 V	1.9 V	Surface Mount	1	-40 °C	85 °C	230 MHz	Yes with Bypass	Crystal, LVCMOS	Yes/No	16-TSSOP
Texas Instruments CDCE925PWG4				PLL Clock Generator	0.173 "	16-TSSOP	4.4 mm	1:5	LVCMOS	1.7 V	1.9 V	Surface Mount	1	-40 °C	85 °C	230 MHz	Yes with Bypass	Crystal, LVCMOS	Yes/No	16-TSSOP

Key Features

• Member of Programmable Clock Generator FamilyCDCEx913: 1-PLL, 3 OutputsCDCEx925: 2-PLL, 5 OutputsCDCEx925: 3-PLL, 7 OutputsCDCEx949: 4-PLL, 9 OutputsIn-System Programmability and EEPROMSerial Programmable Volatile RegisterNonvolatile EEPROM to Store Customer SettingsFlexible Input Clocking ConceptExternal Crystal: 8 MHz to 32 MHzOn-Chip VCXO: Pull Range ±150 ppmSingle-Ended LVCMOS Up to 160 MHzFree Selectable Output Frequency Up to 230 MHzLow-Noise PLL CorePLL Loop Filter Components IntegratedLow Period Jitter (Typical 60 ps)Separate Output Supply PinsCDCE925: 3.3 V and 2.5 VCDCEL925: 1.8 VFlexible Clock DriverThree User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable, or Power DownGenerates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPSGenerates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPsProgrammable SSC ModulationEnables 0-PPM Clock Generation1.8-V Device Power SupplyWide Temperature Range: –40°C to 85°CPackaged in TSSOPDevelopment and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)APPLICATIONSD-TVs, STBs, IP-STBs, DVD Players, DVD Recorders, and PrintersAll other trademarks are the property of their respective ownersMember of Programmable Clock Generator FamilyCDCEx913: 1-PLL, 3 OutputsCDCEx925: 2-PLL, 5 OutputsCDCEx925: 3-PLL, 7 OutputsCDCEx949: 4-PLL, 9 OutputsIn-System Programmability and EEPROMSerial Programmable Volatile RegisterNonvolatile EEPROM to Store Customer SettingsFlexible Input Clocking ConceptExternal Crystal: 8 MHz to 32 MHzOn-Chip VCXO: Pull Range ±150 ppmSingle-Ended LVCMOS Up to 160 MHzFree Selectable Output Frequency Up to 230 MHzLow-Noise PLL CorePLL Loop Filter Components IntegratedLow Period Jitter (Typical 60 ps)Separate Output Supply PinsCDCE925: 3.3 V and 2.5 VCDCEL925: 1.8 VFlexible Clock DriverThree User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable, or Power DownGenerates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPSGenerates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPsProgrammable SSC ModulationEnables 0-PPM Clock Generation1.8-V Device Power SupplyWide Temperature Range: –40°C to 85°CPackaged in TSSOPDevelopment and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)APPLICATIONSD-TVs, STBs, IP-STBs, DVD Players, DVD Recorders, and PrintersAll other trademarks are the property of their respective owners

Description

The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to five output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to two independent configurable PLLs. The CDCEx925 has a separate output supply pin, VDDOUT, which is 1.8 V for CDCEL925 and 2.5 V to 3.3 V for CDCE925. The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, that is, PWM signal. The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth, Ethernet, GPS), or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for example. All PLLs support SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL. The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It is preset to a factory default configuration and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface. Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change the SSC setting for lowering EMI, or other control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so forth. The CDCx925 operates in a 1.8-V environment and in a temperature range of –40°C to 85°C. The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to five output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to two independent configurable PLLs. The CDCEx925 has a separate output supply pin, VDDOUT, which is 1.8 V for CDCEL925 and 2.5 V to 3.3 V for CDCE925. The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, that is, PWM signal. The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth, Ethernet, GPS), or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for example. All PLLs support SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL. The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It is preset to a factory default configuration and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface. Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change the SSC setting for lowering EMI, or other control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so forth. The CDCx925 operates in a 1.8-V environment and in a temperature range of –40°C to 85°C.