CD74HC192 Series
High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous Reset
| Part | Logic Type | Package / Case | Timing | Trigger Type | Number of Bits per Element | Direction | Number of Elements [custom] | Supplier Device Package | Mounting Type | Voltage - Supply [Max] | Voltage - Supply [Min] | Operating Temperature [Min] | Operating Temperature [Max] | Count Rate | Reset | Package / Case [x] | Package / Case [x] | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HC192NSR | Counter, Decade | 16-SOIC (0.209", 5.30mm Width) | Synchronous | Positive Edge | 4 | Down, Up | 1 | 16-SO | Surface Mount | 6 V | 2 V | -55 °C | 125 °C | 24 MHz | Asynchronous | |||
Texas Instruments CD74HC192PWT | Counter, Decade | 16-TSSOP | Synchronous | Positive Edge | 4 | Down, Up | 1 | 16-TSSOP | Surface Mount | 6 V | 2 V | -55 °C | 125 °C | 24 MHz | Asynchronous | 0.173 " | 4.4 mm | |
Texas Instruments CD74HC192E | Counter, Decade | 16-DIP | Synchronous | Positive Edge | 4 | Down, Up | 1 | 16-PDIP | Through Hole | 6 V | 2 V | -55 °C | 125 °C | 24 MHz | Asynchronous | 0.3 in, 7.62 mm | ||
Texas Instruments CD74HC192PWR | Counter, Decade | 16-TSSOP | Synchronous | Positive Edge | 4 | Down, Up | 1 | 16-TSSOP | Surface Mount | 6 V | 2 V | -55 °C | 125 °C | 24 MHz | Asynchronous | 0.173 " | 4.4 mm |
Key Features
• Synchronous Counting and Asynchronous LoadingTwo Outputs for N-Bit CascadingLook-Ahead Carry for High-Speed CountingFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris SemiconductorSynchronous Counting and Asynchronous LoadingTwo Outputs for N-Bit CascadingLook-Ahead Carry for High-Speed CountingFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris Semiconductor
Description
AI
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.