CD74HC192PWT
ActiveTexas Instruments
HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS BCD DECADE UP/DOWN COUNTER WITH ASYNCHRONOUS RESET
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CD74HC192PWT
ActiveTexas Instruments
HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS BCD DECADE UP/DOWN COUNTER WITH ASYNCHRONOUS RESET
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CD74HC192PWT | 74HC192 Series |
|---|---|---|
| Count Rate | 24 MHz | 24 MHz |
| Direction | Down, Up | Down, Up |
| Logic Type | Decade, Counter | Decade, Counter |
| Mounting Type | Surface Mount | Surface Mount, Through Hole |
| Number of Bits per Element | 4 | 4 |
| Number of Elements [custom] | 1 | 1 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 °C | -55 °C |
| Package / Case | 16-TSSOP | 16-SOIC (0.209", 5.30mm Width), 16-TSSOP, 16-DIP |
| Package / Case | - | 0.3 - 7.62 in |
| Package / Case [x] | 0.173 " | 0.173 " |
| Package / Case [x] | 4.4 mm | 4.4 mm |
| Reset | Asynchronous | Asynchronous |
| Supplier Device Package | 16-TSSOP | 16-SO, 16-TSSOP, 16-PDIP |
| Timing | Synchronous | Synchronous |
| Trigger Type | Positive Edge | Positive Edge |
| Voltage - Supply [Max] | 6 V | 6 V |
| Voltage - Supply [Min] | 2 V | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
74HC192 Series
IC DECADE COUNTER 4-BIT 16SO
| Part | Timing | Supplier Device Package | Reset | Logic Type | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Direction | Number of Bits per Element | Voltage - Supply [Max] | Voltage - Supply [Min] | Mounting Type | Number of Elements [custom] | Count Rate | Trigger Type | Package / Case [x] | Package / Case [x] | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Synchronous | 16-SO | Asynchronous | Counter, Decade | 16-SOIC (0.209", 5.30mm Width) | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Surface Mount | 1 | 24 MHz | Positive Edge | ||||
Synchronous | 16-TSSOP | Asynchronous | Counter, Decade | 16-TSSOP | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Surface Mount | 1 | 24 MHz | Positive Edge | 0.173 " | 4.4 mm | ||
Synchronous | 16-TSSOP | Asynchronous | Counter, Decade | 16-TSSOP | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Surface Mount | 1 | 24 MHz | Positive Edge | 0.173 " | 4.4 mm | ||
Texas Instruments CD74HC192PWTThe ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. | Synchronous | 16-TSSOP | Asynchronous | Counter, Decade | 16-TSSOP | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Surface Mount | 1 | 24 MHz | Positive Edge | 0.173 " | 4.4 mm | |
Synchronous | 16-TSSOP | Asynchronous | Counter, Decade | 16-TSSOP | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Surface Mount | 1 | 24 MHz | Positive Edge | 0.173 " | 4.4 mm | ||
Texas Instruments CD74HC192PWRThe ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. | Synchronous | 16-TSSOP | Asynchronous | Counter, Decade | 16-TSSOP | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Surface Mount | 1 | 24 MHz | Positive Edge | 0.173 " | 4.4 mm | |
Texas Instruments CD74HC192EThe ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. | Synchronous | 16-PDIP | Asynchronous | Counter, Decade | 16-DIP | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Through Hole | 1 | 24 MHz | Positive Edge | 0.3 in, 7.62 mm | ||
Texas Instruments CD74HC192NSRThe ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. | Synchronous | 16-SO | Asynchronous | Counter, Decade | 16-SOIC (0.209", 5.30mm Width) | -55 °C | 125 °C | Down, Up | 4 | 6 V | 2 V | Surface Mount | 1 | 24 MHz | Positive Edge |
Description
General part information
74HC192 Series
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
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