SN74AUP2G125 Series

2-ch, 0.8-V to 3.6-V low power buffers with 3-state outputs

Catalog

2-ch, 0.8-V to 3.6-V low power buffers with 3-state outputs

Part	Current - Output Low	Current - Output High	Number of Elements	Logic Type	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Number of Bits per Element	Package / Case	Output Type	Operating Temperature (Max)	Operating Temperature (Min)	Package Name	Mounting Type	Package Length	Package Width
Texas Instruments SN74AUP2G125YFPR	4 mA	4 mA	2	Buffer Non-Inverting	0.8 V	3.6 V	1 bits	8-XFBGA DSBGA	3-State	85 °C	-40 °C	8-DSBGA	Surface Mount
Texas Instruments SN74AUP2G125DQER	4 mA	4 mA	2	Buffer Non-Inverting	0.8 V	3.6 V	1 bits	8-XFDFN	3-State	85 °C	-40 °C	8-X2SON	Surface Mount	1.4 mm	1 mm
Texas Instruments SN74AUP2G125RSER	4 mA	4 mA	2	Buffer Non-Inverting	0.8 V	3.6 V	1 bits	8-UFQFN	3-State	85 °C	-40 °C	8-UQFN	Surface Mount	1.5 mm	1.5 mm
Texas Instruments SN74AUP2G125YZPR	4 mA	4 mA	2	Buffer Non-Inverting	0.8 V	3.6 V	1 bits	8-XFBGA DSBGA	3-State	85 °C	-40 °C	8-DSBGA	Surface Mount
Texas Instruments SN74AUP2G125DCUR	4 mA	4 mA	2	Buffer Non-Inverting	0.8 V	3.6 V	1 bits		3-State	85 °C	-40 °C	8-VFSOP 8-VSSOP	Surface Mount	0.091 in	2.3 mm

Catalog

2-ch, 0.8-V to 3.6-V low power buffers with 3-state outputs

Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2). The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCCoperation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2). The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCCoperation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.