CDCVF2510 Series

3.3-V phase-lock loop clock driver with power down mode

Link to Manufacturer Page: https://www.ti.com/

Catalog

3.3-V phase-lock loop clock driver with power down mode

Part	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	PLL	Type	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Number of Circuits	Frequency - Max [Max]	Output	Package / Case [y]	Package / Case [y]	Package / Case	Operating Temperature [Max]
Texas Instruments CDCVF2510APW	11	2	Yes with Bypass	PLL Clock Driver	24-TSSOP	3.6 V	3 V	Surface Mount	1	175 MHz	LVTTL	4.4 mm	0.173 "	24-TSSOP	85 °C
Texas Instruments CDCVF2510PWG4	11	2	Yes with Bypass	PLL Clock Driver	24-TSSOP	3.6 V	3 V	Surface Mount	1	175 MHz	LVTTL	4.4 mm	0.173 "	24-TSSOP	85 °C
Texas Instruments CDCVF2510APWR	11	2	Yes with Bypass	PLL Clock Driver	24-TSSOP	3.6 V	3 V	Surface Mount	1	175 MHz	LVTTL	4.4 mm	0.173 "	24-TSSOP	85 °C
Texas Instruments CDCVF2510PWR	11	2	Yes with Bypass	PLL Clock Driver	24-TSSOP	3.6 V	3 V	Surface Mount	1	175 MHz	LVTTL	4.4 mm	0.173 "	24-TSSOP	85 °C
Texas Instruments CDCVF2510PW	11	2	Yes with Bypass	PLL Clock Driver	24-TSSOP	3.6 V	3 V	Surface Mount	1	175 MHz	LVTTL	4.4 mm	0.173 "	24-TSSOP	85 °C

Key Features

• Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1Spread Spectrum Clock CompatibleOperating Frequency 20 MHz to 175 MHzStatic Phase Error Distribution at 66 MHz to 166 MHz is ±125 psJitter (cyc–cyc) at 66 MHz to 166 MHz is |70| psAdvanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 DevicesAuto Frequency Detection to Disable Device (Power-Down Mode)Available in Plastic 24-Pin TSSOPDistributes One Clock Input to One Bank of 10 OutputsExternal Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input25-On-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 VAPPLICATIONSDRAM ApplicationsPLL Based Clock DistributorsNon-PLL Clock BufferDesigned to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1Spread Spectrum Clock CompatibleOperating Frequency 20 MHz to 175 MHzStatic Phase Error Distribution at 66 MHz to 166 MHz is ±125 psJitter (cyc–cyc) at 66 MHz to 166 MHz is |70| psAdvanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 DevicesAuto Frequency Detection to Disable Device (Power-Down Mode)Available in Plastic 24-Pin TSSOPDistributes One Clock Input to One Bank of 10 OutputsExternal Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input25-On-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 VAPPLICATIONSDRAM ApplicationsPLL Based Clock DistributorsNon-PLL Clock Buffer

Description

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510A operates at a 3.3-V VCCand also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. The device automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state. Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCCto ground to use as a simple clock buffer. The CDCVF2510A is characterized for operation from 0°C to 85°C. The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510A operates at a 3.3-V VCCand also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. The device automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state. Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCCto ground to use as a simple clock buffer. The CDCVF2510A is characterized for operation from 0°C to 85°C.