CDCM7005-SP Series

Radiation-hardened-assured (RHA) 3.3-V high-performance clock jitter cleaner and synchronizer

Link to Manufacturer Page: https://www.ti.com/

Catalog

Radiation-hardened-assured (RHA) 3.3-V high-performance clock jitter cleaner and synchronizer

Part	Package / Case	Output	Mounting Type	PLL	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Operating Temperature [Min]	Operating Temperature [Max]	Input	Number of Circuits	Frequency - Max [Max]	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]
Texas Instruments CDCM7005HFG/EM	52-CFlatPack	LVCMOS, LVPECL	Surface Mount	Yes with Bypass	52-CFP	3.6 V	3 V			-40 °C	85 °C	LVCMOS, LVPECL	1	1.5 GHz	3	10

Key Features

• High Performance LVPECL and LVCMOS PLLClock SynchronizerTwo Reference Clock Inputs (Primary andSecondary Clock) for Redundancy SupportWith Manual or Automatic SelectionAccepts LVCMOS Input Frequencies Up to200 MHzVCXO_IN Clock is Synchronized to One of theTwo Reference ClocksVCXO_IN Frequencies Up to 2 GHz (LVPECL)Outputs can be a Combination of LVPECL andLVCMOS (Up to Five Differential LVPECLOutputs or Up to 10 LVCMOS Outputs)Output Frequency is Selectable by x1, /2, /3, /4,/6, /8, /16 on Each OutputIndividuallyEfficient Jitter Cleaning from Low PLL LoopBandwidthLow Phase Noise PLL CoreProgrammable Phase Offset (PRI_REF andSEC_REF to Outputs)Wide Charge Pump Current Range From200 µA to 3 mAAnalog and Digital PLL Lock IndicationProvides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)Frequency Hold Over Mode Improves Fail-SafeOperationPower-Up Control Forces LVPECL Outputs to Tri-State at VCC< 1.5 VSPI Controllable Device Setting3.3-V Power SupplyHigh-Performance 52 Pin Ceramic Quad FlatPack (HFG)Rad-Tolerant : 50 kRad (Si) TIDQML-V Qualified, SMD 5962-07230Military Temperature Range: –55°C to 125°C TcaseEngineering Evaluation (/EM) Samples areAvailable(1)High Performance LVPECL and LVCMOS PLLClock SynchronizerTwo Reference Clock Inputs (Primary andSecondary Clock) for Redundancy SupportWith Manual or Automatic SelectionAccepts LVCMOS Input Frequencies Up to200 MHzVCXO_IN Clock is Synchronized to One of theTwo Reference ClocksVCXO_IN Frequencies Up to 2 GHz (LVPECL)Outputs can be a Combination of LVPECL andLVCMOS (Up to Five Differential LVPECLOutputs or Up to 10 LVCMOS Outputs)Output Frequency is Selectable by x1, /2, /3, /4,/6, /8, /16 on Each OutputIndividuallyEfficient Jitter Cleaning from Low PLL LoopBandwidthLow Phase Noise PLL CoreProgrammable Phase Offset (PRI_REF andSEC_REF to Outputs)Wide Charge Pump Current Range From200 µA to 3 mAAnalog and Digital PLL Lock IndicationProvides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)Frequency Hold Over Mode Improves Fail-SafeOperationPower-Up Control Forces LVPECL Outputs to Tri-State at VCC< 1.5 VSPI Controllable Device Setting3.3-V Power SupplyHigh-Performance 52 Pin Ceramic Quad FlatPack (HFG)Rad-Tolerant : 50 kRad (Si) TIDQML-V Qualified, SMD 5962-07230Military Temperature Range: –55°C to 125°C TcaseEngineering Evaluation (/EM) Samples areAvailable(1)

Description

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M. VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase). The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M. VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).