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ADC32RF45 Series

Dual-channel, 14-bit, 3-GSPS, RF-sampling analog-to-digital converter (ADC)

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

Dual-channel, 14-bit, 3-GSPS, RF-sampling analog-to-digital converter (ADC)

PartArchitectureVoltage - Supply, Digital [Min]Voltage - Supply, Digital [Max]Supplier Device PackageInput TypeNumber of BitsVoltage - Supply, Analog [Min]Voltage - Supply, Analog [Max]Number of InputsNumber of A/D ConvertersOperating Temperature [Max]Operating Temperature [Min]Package / CaseData InterfaceReference TypeMounting TypeSampling Rate (Per Second)
Texas Instruments
ADC32RF45IRMP
Pipelined
1.1 V
1.2 V
72-VQFN (10x10)
Differential
14
1.1 V
2 V
2
8
85 °C
-40 °C
72-VFQFN Exposed Pad
JESD204B
Internal
Surface Mount
3 G
Texas Instruments
ADC32RF45IRMPT
Pipelined
1.1 V
1.2 V
72-VQFN (10x10)
Differential
14
1.1 V
2 V
2
8
85 °C
-40 °C
72-VFQFN Exposed Pad
JESD204B
Internal
Surface Mount
3 G

Key Features

14-Bit, Dual-Channel, 3.0-GSPS ADCNoise Floor: –155 dBFS/HzRF Input Supports Up to 4.0 GHzAperture Jitter: 90 fSChannel Isolation: 95 dB at fIN= 1.8 GHzSpectral Performance (fIN= 900 MHz, –2 dBFS):SNR: 60.9 dBFSSFDR: 67-dBc HD2, HD3SFDR: 77-dBc Worst SpurSpectral Performance (fIN= 1.78 GHz, –2 dBFS):SNR: 58.8 dBFSSFDR: 66-dBc HD2, HD3SFDR: 75-dBc Worst SpurOn-Chip Digital Down-Converters:Up to 4 DDCs (Dual-Band Mode)Up to 3 Independent NCOs per DDCOn-Chip Input Clamp for Overvoltage ProtectionProgrammable On-Chip Power Detectors with Alarm Pins for AGC SupportOn-Chip DitherOn-Chip Input TerminationInput Full-Scale: 1.35 VPPSupport for Multi-Chip SynchronizationJESD204B Interface:Subclass 1-Based Deterministic Latency4 Lanes Per Channel at 12.5 GbpsPower Dissipation: 3.2 W/Ch at 3.0 GSPS72-Pin VQFN Package (10 mm × 10 mm)14-Bit, Dual-Channel, 3.0-GSPS ADCNoise Floor: –155 dBFS/HzRF Input Supports Up to 4.0 GHzAperture Jitter: 90 fSChannel Isolation: 95 dB at fIN= 1.8 GHzSpectral Performance (fIN= 900 MHz, –2 dBFS):SNR: 60.9 dBFSSFDR: 67-dBc HD2, HD3SFDR: 77-dBc Worst SpurSpectral Performance (fIN= 1.78 GHz, –2 dBFS):SNR: 58.8 dBFSSFDR: 66-dBc HD2, HD3SFDR: 75-dBc Worst SpurOn-Chip Digital Down-Converters:Up to 4 DDCs (Dual-Band Mode)Up to 3 Independent NCOs per DDCOn-Chip Input Clamp for Overvoltage ProtectionProgrammable On-Chip Power Detectors with Alarm Pins for AGC SupportOn-Chip DitherOn-Chip Input TerminationInput Full-Scale: 1.35 VPPSupport for Multi-Chip SynchronizationJESD204B Interface:Subclass 1-Based Deterministic Latency4 Lanes Per Channel at 12.5 GbpsPower Dissipation: 3.2 W/Ch at 3.0 GSPS72-Pin VQFN Package (10 mm × 10 mm)

Description

AI
The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms. The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C). The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms. The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).