CDCVF855 Series
2.5-V phase lock loop DDR clock driver
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
2.5-V phase lock loop DDR clock driver
| Part | Mounting Type | Output | Voltage - Supply [Max] | Voltage - Supply [Min] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Package / Case | Package / Case | Package / Case | Number of Circuits | Supplier Device Package | Type | PLL | Frequency - Max [Max] | Operating Temperature [Min] | Operating Temperature [Max] | Input | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Divider/Multiplier [custom] | Divider/Multiplier [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCVF855PWR | Surface Mount | SSTL-2 | 2.7 V | 2.3 V | 28-TSSOP | 4.4 mm | 0.173 in | 1 | 28-TSSOP | PLL Clock Driver | Yes with Bypass | 220 MHz | -40 °C | 85 °C | SSTL-2 | 2 | 5 | ||||
Texas Instruments CDCVF855PWRG4 | Surface Mount | SSTL-2 | 2.7 V | 2.3 V | 28-TSSOP | 4.4 mm | 0.173 in | 1 | 28-TSSOP | PLL Clock Driver | Yes with Bypass | 220 MHz | -40 °C | 85 °C | SSTL-2 | 2 | 5 | ||||
Texas Instruments CDCVF855PWG4 | Surface Mount | SSTL-2 | 2.7 V | 2.3 V | 28-TSSOP | 4.4 mm | 0.173 in | 1 | 28-TSSOP | PLL Clock Driver | Yes with Bypass | 220 MHz | -40 °C | 85 °C | SSTL-2 | 2 | 5 | ||||
Texas Instruments CDCVF855PW | Surface Mount | SSTL-2 | 2.7 V | 2.3 V | 28-TSSOP | 4.4 mm | 0.173 in | 1 | 28-TSSOP | PLL Clock Driver | Yes with Bypass | 220 MHz | -40 °C | 85 °C | SSTL-2 | 2 | 5 |
Key Features
• Spread-Spectrum Clock CompatibleOperating Frequency: 60 MHz to 220 MHzLow Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200 MHz)Low Static Phase Offset: ±50 psLow Jitter (Period): ±60 ps (±30 ps at 200 MHz)1-to-4 Differential Clock Distribution (SSTL2)Best in Class for VOX= VDD/2 ±0.1 VOperates From Dual 2.6-V or 2.5-V SuppliesAvailable in a 28-Pin TSSOP PackageConsumes < 100-µA Quiescent CurrentExternal Feedback Pins (FBIN,FBIN) Are Used to Synchronize the Outputs to the Input ClocksMeets/Exceeds JEDEC Standard (JESD82-1) For DDRI-200/266/333 SpecificationMeets/Exceeds Proposed DDRI-400 Specification (JESD82-1A)Enters Low-Power Mode When No CLK Input Signal Is Applied orPWRDWNIs LowAPPLICATIONSDDR Memory Modules (DDR400/333/266/200)Zero-Delay Fan-Out BufferSpread-Spectrum Clock CompatibleOperating Frequency: 60 MHz to 220 MHzLow Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200 MHz)Low Static Phase Offset: ±50 psLow Jitter (Period): ±60 ps (±30 ps at 200 MHz)1-to-4 Differential Clock Distribution (SSTL2)Best in Class for VOX= VDD/2 ±0.1 VOperates From Dual 2.6-V or 2.5-V SuppliesAvailable in a 28-Pin TSSOP PackageConsumes < 100-µA Quiescent CurrentExternal Feedback Pins (FBIN,FBIN) Are Used to Synchronize the Outputs to the Input ClocksMeets/Exceeds JEDEC Standard (JESD82-1) For DDRI-200/266/333 SpecificationMeets/Exceeds Proposed DDRI-400 Specification (JESD82-1A)Enters Low-Power Mode When No CLK Input Signal Is Applied orPWRDWNIs LowAPPLICATIONSDDR Memory Modules (DDR400/333/266/200)Zero-Delay Fan-Out Buffer
Description
AI
The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK,CLK) to 4 differential pairs of clock outputs (Y[0:3],Y[0:3]) and one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the clock inputs (CLK,CLK), the feedback clocks (FBIN,FBIN), and the analog power input (AVDD). WhenPWRDWNis high, the outputs switch in phase and frequency with CLK. WhenPWRDWNis low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency-detection circuit detects the low-frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.
When AVDDis strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF855 is also able to track spread-spectrum clocking for reduced EMI.
Because the CDCVF855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF855 is characterized for both commercial and industrial temperature ranges.
The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK,CLK) to 4 differential pairs of clock outputs (Y[0:3],Y[0:3]) and one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the clock inputs (CLK,CLK), the feedback clocks (FBIN,FBIN), and the analog power input (AVDD). WhenPWRDWNis high, the outputs switch in phase and frequency with CLK. WhenPWRDWNis low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency-detection circuit detects the low-frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.
When AVDDis strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF855 is also able to track spread-spectrum clocking for reduced EMI.
Because the CDCVF855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF855 is characterized for both commercial and industrial temperature ranges.