CD54HCT75 Series
High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch
| Part | Package / Case | Delay Time - Propagation | Output Type | Circuit | Logic Type | Current - Output High, Low | Supplier Device Package | Mounting Type | Independent Circuits | Voltage - Supply [Max] | Voltage - Supply [Min] | Operating Temperature [Min] | Operating Temperature [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HCT75F3A | 16-CDIP (0.300", 7.62mm) | 10 ns | Complementary | 2:2 | D-Type Transparent Latch | 4 mA, 4 mA | 16-CDIP | Through Hole | 2 | 5.5 V | 4.5 V | -55 °C | 125 °C |
Key Features
• True and Complementary OutputsBuffered Inputs and OutputsFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris SemiconductorTrue and Complementary OutputsBuffered Inputs and OutputsFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris Semiconductor
Description
AI
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.