CD74ACT109 Series
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset
| Part | Trigger Type | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Max Propagation Delay @ V, Max CL | Mounting Type | Package / Case | Package / Case | Number of Bits per Element | Output Type | Current - Quiescent (Iq) | Voltage - Supply [Max] | Voltage - Supply [Min] | Type | Function | Clock Frequency | Operating Temperature [Min] | Operating Temperature [Max] | Number of Elements [custom] | Supplier Device Package | Input Capacitance |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74ACT109M | Positive Edge | 24 mA | 24 mA | 10.3 ns | Surface Mount | 16-SOIC | 0.154 in, 3.9 mm Width | 1 | Complementary | 4 çA | 5.5 V | 4.5 V | JK Type | Reset, Set(Preset) | 100 MHz | -55 C | 125 °C | 2 | 16-SOIC | 10 pF |
Texas Instruments CD74ACT109M96 | Positive Edge | 24 mA | 24 mA | 10.3 ns | Surface Mount | 16-SOIC | 0.154 in, 3.9 mm Width | 1 | Complementary | 4 çA | 5.5 V | 4.5 V | JK Type | Reset, Set(Preset) | 100 MHz | -55 C | 125 °C | 2 | 16-SOIC | 10 pF |
Texas Instruments CD74ACT109E | Positive Edge | 24 mA | 24 mA | 10.3 ns | Through Hole | 16-DIP | 0.3 in, 7.62 mm | 1 | Complementary | 4 çA | 5.5 V | 4.5 V | JK Type | Reset, Set(Preset) | 100 MHz | -55 C | 125 °C | 2 | 16-PDIP | 10 pF |
Key Features
• Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
Description
AI
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.