CDCLVD1204 Series
Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer
| Part | Operating Temperature [Min] | Operating Temperature [Max] | Output | Package / Case | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Mounting Type | Input | Frequency - Max [Max] | Supplier Device Package | Number of Circuits | Voltage - Supply [Min] | Voltage - Supply [Max] | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVD1204RGTT | -40 °C | 85 °C | LVDS | 16-VFQFN Exposed Pad | Surface Mount | LVCMOS, LVDS, LVPECL | 800 MHz | 16-VQFN (3x3) | 1 | 2.375 V | 2.625 V | 4 | 2 | Fanout Buffer (Distribution), Multiplexer | ||
Texas Instruments CDCLVD1204RGTR | -40 °C | 85 °C | LVDS | 16-VFQFN Exposed Pad | Surface Mount | LVCMOS, LVDS, LVPECL | 800 MHz | 16-VQFN (3x3) | 1 | 2.375 V | 2.625 V | 4 | 2 | Fanout Buffer (Distribution), Multiplexer |
Key Features
• 2:4 Differential BufferLow Additive Jitter: <300 fs RMS in 10-kHz to 20-MHzLow Output Skew of 20 ps (Maximum)Universal Inputs Accept LVDS, LVPECL, and LVCMOSSelectable Clock Inputs Through Control Pin4 LVDS Outputs, ANSI EAI/TIA-644A Standard CompatibleClock Frequency: Up to 800 MHzDevice Power Supply: 2.375 V to 2.625 VLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range: –40°C to 85°CPackaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)ESD Protection Exceeds 3 kV HBM, 1 kV CDMAPPLICATIONSTelecommunications and NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose ClockingAll other trademarks are the property of their respective owners2:4 Differential BufferLow Additive Jitter: <300 fs RMS in 10-kHz to 20-MHzLow Output Skew of 20 ps (Maximum)Universal Inputs Accept LVDS, LVPECL, and LVCMOSSelectable Clock Inputs Through Control Pin4 LVDS Outputs, ANSI EAI/TIA-644A Standard CompatibleClock Frequency: Up to 800 MHzDevice Power Supply: 2.375 V to 2.625 VLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range: –40°C to 85°CPackaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)ESD Protection Exceeds 3 kV HBM, 1 kV CDMAPPLICATIONSTelecommunications and NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose ClockingAll other trademarks are the property of their respective owners
Description
AI
The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.
The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.