54FCT841 Series

10-Bit Bus-Interface D-Type Latches with 3-State Outputs

Catalog

10-Bit Bus-Interface D-Type Latches with 3-State Outputs

Part	Delay Time - Propagation	Operating Temperature [Min]	Operating Temperature [Max]	Output Type	Package / Case	Circuit	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Independent Circuits	Logic Type	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]
Texas Instruments CY54FCT841ATDMB	13 ns	-55 °C	125 °C	Non-Inverted, Tri-State	24-CDIP	10:10	24-CDIP	4.5 V	5.5 V	1	D-Type Transparent Latch	Through Hole	12 mA	32 mA

Catalog

10-Bit Bus-Interface D-Type Latches with 3-State Outputs

Key Features

• Function, Pinout, and Drive Compatible With FCT, F, and AM29841 LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Fully Compatible With TTL Input and Output Logic LevelsHigh-Speed Parallel LatchesBuffered Common Latch-Enable Input3-State OutputsCY54FCT841T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT841T64-mA Output Sink Current32-mA Output Source CurrentFunction, Pinout, and Drive Compatible With FCT, F, and AM29841 LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Fully Compatible With TTL Input and Output Logic LevelsHigh-Speed Parallel LatchesBuffered Common Latch-Enable Input3-State OutputsCY54FCT841T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT841T64-mA Output Sink Current32-mA Output Source Current

Description

The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function. The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function. The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.