Technical Specifications
Parameters and characteristics for this part
| Specification | STM32L552RCT3 |
|---|---|
| Connectivity | SPI, I2C, MMC/SD, LINbus, UART/USART, QSPI, IrDA, CANbus, USB, SAI |
| Core Processor | ARM® Cortex®-M33 |
| Core Size | 32-Bit |
| Data Converters | A/D 16x12b SAR, D/A 2x12b |
| Mounting Type | Surface Mount |
| Number of I/O | 52 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | External, Internal |
| Package / Case | 64-LQFP |
| Peripherals | Temp Sensor, DMA, Brown-out Detect/Reset, WDT, PWM, POR |
| Program Memory Size | 256 KB |
| Program Memory Type | FLASH |
| RAM Size | 256 K |
| Speed | 110 MHz |
| Supplier Device Package | 64-LQFP (10x10) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 960 | $ 5.47 | |
Description
General part information
NUCLEO-L552ZE-Q Series
The STM32L552xx devices are an ultra-low-power microcontrollers family (STM32L5 Series) based on the high-performance Arm®Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 110 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports all the Arm®single-precision data-processing instructions and all the data types. The Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), an Octo-SPI Flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources