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SN74HCT74DR - 14-SOIC

SN74HCT74DR

Active
Texas Instruments

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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SN74HCT74DR - 14-SOIC

SN74HCT74DR

Active
Texas Instruments

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationSN74HCT74DRSN74HCT74 Series
Clock Frequency46 MHz46 MHz
Current - Output High, Low4 mA, 4 mA4 mA
Current - Quiescent (Iq)4 çA4 çA
FunctionReset, Set(Preset)Reset, Set(Preset)
Input Capacitance3 pF3 pF
Max Propagation Delay @ V, Max CL18 ns18 - 25 ns
Mounting TypeSurface MountSurface Mount, Through Hole
Number of Bits per Element11
Number of Elements [custom]22
Operating Temperature [Max]85 °C85 °C
Operating Temperature [Min]-40 °C-40 °C
Output TypeComplementaryComplementary
Package / Case3.9 mm3.9 - 7.62 mm
Package / Case0.154 in0.154 - 5.3 in
Package / Case14-SOIC14-SOIC, 14-DIP, 14-SSOP, 14-TSSOP
Package / Case-5.3 mm
Package / Case-0.209 in
Package / Case-0.209 in
Package / Case-0.173 in
Package / Case-4.4 mm
Supplier Device Package-14-SO, 14-SSOP, 14-TSSOP
Trigger TypePositive EdgePositive Edge
TypeD-TypeD-Type
Voltage - Supply [Max]5.5 V5.5 V
Voltage - Supply [Min]4.5 V4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.37
10$ 0.30
25$ 0.27
100$ 0.20
250$ 0.18
500$ 0.15
1000$ 0.11
Digi-Reel® 1$ 0.37
10$ 0.30
25$ 0.27
100$ 0.20
250$ 0.18
500$ 0.15
1000$ 0.11
Tape & Reel (TR) 2500$ 0.10
5000$ 0.10
12500$ 0.09
25000$ 0.08
62500$ 0.08
125000$ 0.08
Texas InstrumentsLARGE T&R 1$ 0.20
100$ 0.13
250$ 0.10
1000$ 0.07

SN74HCT74 Series

Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

PartSupplier Device PackageTypePackage / Case [y]Package / Case [y]Package / CaseCurrent - Quiescent (Iq)Mounting TypeOperating Temperature [Max]Operating Temperature [Min]Trigger TypeNumber of Bits per ElementCurrent - Output High, LowMax Propagation Delay @ V, Max CLClock FrequencyOutput TypeFunctionInput CapacitanceNumber of Elements [custom]Voltage - Supply [Max]Voltage - Supply [Min]Package / CasePackage / CasePackage / CasePackage / Case [custom]Package / Case [custom]
Texas Instruments
SN74HCT74NSR
14-SO
D-Type
5.3 mm
0.209 in
14-SOIC
4 çA
Surface Mount
85 °C
-40 °C
Positive Edge
1
4 mA, 4 mA
25 ns
46 MHz
Complementary
Reset, Set(Preset)
3 pF
2
5.5 V
4.5 V
Texas Instruments
SN74HCT74N
D-Type
14-DIP
4 çA
Through Hole
85 °C
-40 °C
Positive Edge
1
4 mA, 4 mA
25 ns
46 MHz
Complementary
Reset, Set(Preset)
3 pF
2
5.5 V
4.5 V
7.62 mm
0.3 in
Texas Instruments
SN74HCT74DBR
14-SSOP
D-Type
14-SSOP
4 çA
Surface Mount
85 °C
-40 °C
Positive Edge
1
4 mA, 4 mA
25 ns
46 MHz
Complementary
Reset, Set(Preset)
3 pF
2
5.5 V
4.5 V
5.3 mm
0.209 in
Texas Instruments
SN74HCT74PWR
14-TSSOP
D-Type
14-TSSOP
4 çA
Surface Mount
85 °C
-40 °C
Positive Edge
1
4 mA, 4 mA
25 ns
46 MHz
Complementary
Reset, Set(Preset)
3 pF
2
5.5 V
4.5 V
0.173 in
4.4 mm
Texas Instruments
SN74HCT74DRE4
D-Type
14-SOIC
4 çA
Surface Mount
85 °C
-40 °C
Positive Edge
1
4 mA, 4 mA
25 ns
46 MHz
Complementary
Reset, Set(Preset)
3 pF
2
5.5 V
4.5 V
3.9 mm
0.154 in
Texas Instruments
SN74HCT74DR
D-Type
14-SOIC
4 çA
Surface Mount
85 °C
-40 °C
Positive Edge
1
4 mA, 4 mA
18 ns
46 MHz
Complementary
Reset, Set(Preset)
3 pF
2
5.5 V
4.5 V
3.9 mm
0.154 in
Texas Instruments
SN74HCT74PW
14-TSSOP
D-Type
14-TSSOP
4 çA
Surface Mount
85 °C
-40 °C
Positive Edge
1
4 mA, 4 mA
25 ns
46 MHz
Complementary
Reset, Set(Preset)
3 pF
2
5.5 V
4.5 V
0.173 in
4.4 mm

Description

General part information

SN74HCT74 Series

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.