SN74HCT74 Series
Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset
| Part | Supplier Device Package | Type | Package / Case [y] | Package / Case [y] | Package / Case | Current - Quiescent (Iq) | Mounting Type | Operating Temperature [Max] | Operating Temperature [Min] | Trigger Type | Number of Bits per Element | Current - Output High, Low | Max Propagation Delay @ V, Max CL | Clock Frequency | Output Type | Function | Input Capacitance | Number of Elements [custom] | Voltage - Supply [Max] | Voltage - Supply [Min] | Package / Case | Package / Case | Package / Case | Package / Case [custom] | Package / Case [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74HCT74NSR | 14-SO | D-Type | 5.3 mm | 0.209 in | 14-SOIC | 4 çA | Surface Mount | 85 °C | -40 °C | Positive Edge | 1 | 4 mA, 4 mA | 25 ns | 46 MHz | Complementary | Reset, Set(Preset) | 3 pF | 2 | 5.5 V | 4.5 V | |||||
Texas Instruments SN74HCT74N | D-Type | 14-DIP | 4 çA | Through Hole | 85 °C | -40 °C | Positive Edge | 1 | 4 mA, 4 mA | 25 ns | 46 MHz | Complementary | Reset, Set(Preset) | 3 pF | 2 | 5.5 V | 4.5 V | 7.62 mm | 0.3 in | ||||||
Texas Instruments SN74HCT74DBR | 14-SSOP | D-Type | 14-SSOP | 4 çA | Surface Mount | 85 °C | -40 °C | Positive Edge | 1 | 4 mA, 4 mA | 25 ns | 46 MHz | Complementary | Reset, Set(Preset) | 3 pF | 2 | 5.5 V | 4.5 V | 5.3 mm | 0.209 in | |||||
Texas Instruments SN74HCT74PWR | 14-TSSOP | D-Type | 14-TSSOP | 4 çA | Surface Mount | 85 °C | -40 °C | Positive Edge | 1 | 4 mA, 4 mA | 25 ns | 46 MHz | Complementary | Reset, Set(Preset) | 3 pF | 2 | 5.5 V | 4.5 V | 0.173 in | 4.4 mm | |||||
Texas Instruments SN74HCT74DRE4 | D-Type | 14-SOIC | 4 çA | Surface Mount | 85 °C | -40 °C | Positive Edge | 1 | 4 mA, 4 mA | 25 ns | 46 MHz | Complementary | Reset, Set(Preset) | 3 pF | 2 | 5.5 V | 4.5 V | 3.9 mm | 0.154 in | ||||||
Texas Instruments SN74HCT74DR | D-Type | 14-SOIC | 4 çA | Surface Mount | 85 °C | -40 °C | Positive Edge | 1 | 4 mA, 4 mA | 18 ns | 46 MHz | Complementary | Reset, Set(Preset) | 3 pF | 2 | 5.5 V | 4.5 V | 3.9 mm | 0.154 in | ||||||
Texas Instruments SN74HCT74PW | 14-TSSOP | D-Type | 14-TSSOP | 4 çA | Surface Mount | 85 °C | -40 °C | Positive Edge | 1 | 4 mA, 4 mA | 25 ns | 46 MHz | Complementary | Reset, Set(Preset) | 3 pF | 2 | 5.5 V | 4.5 V | 0.173 in | 4.4 mm |
Key Features
• Operating voltage range of 4.5 V to 5.5 VOutputs can drive up to 10 LSTTL loadsLow power consumption, 40-µA max I CCTypical t pd = 17 ns±4-mA output drive at 5 VLow input current of 1 µA maxInputs are TTL-voltage compatibleOperating voltage range of 4.5 V to 5.5 VOutputs can drive up to 10 LSTTL loadsLow power consumption, 40-µA max I CCTypical t pd = 17 ns±4-mA output drive at 5 VLow input current of 1 µA maxInputs are TTL-voltage compatible
Description
AI
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.