Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CD74HC4515EN | 74HC4515 Series |
|---|---|---|
| Circuit | 1 | 1 |
| Circuit [custom] | 4:16 | 4:16 |
| Current - Output High, Low | 5.2 mA, 5.2 mA | 5.2 mA |
| Independent Circuits | 1 | 1 |
| Mounting Type | Through Hole | Surface Mount, Through Hole |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 °C | -55 °C |
| Package / Case | 24-DIP | 24-SOIC, 24-DIP |
| Package / Case | 7.62 mm, 0.3 in | 0.3 - 7.62 mm |
| Package / Case | - | 7.5 mm |
| Package / Case | - | 0.295 in |
| Package / Case | - | 15.24 mm |
| Package / Case | - | 0.6 in |
| Supplier Device Package | 24-PDIP | 24-SOIC, 24-PDIP |
| Type | Decoder/Demultiplexer | Decoder/Demultiplexer |
| Voltage - Supply [Max] | 6 V | 6 V |
| Voltage - Supply [Min] | 2 V | 2 V |
| Voltage Supply Source | Single Supply | Single Supply |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
74HC4515 Series
High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input Latches
| Part | Operating Temperature [Min] | Operating Temperature [Max] | Voltage Supply Source | Voltage - Supply [Min] | Voltage - Supply [Max] | Type | Mounting Type | Circuit [custom] | Circuit | Independent Circuits | Current - Output High, Low | Package / Case [y] | Package / Case [x] | Package / Case | Supplier Device Package | Package / Case | Package / Case | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HC4515MThe CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4-to-16 line decoder. The selected output is enabled by a low on the enable input (E\). A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using the E\ input as the data input and the select inputs (A0-A3) as addresses. This E\ input also serves as a chip select when these devices are cascaded.
When Latch Enable (LE\) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads.
The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4-to-16 line decoder. The selected output is enabled by a low on the enable input (E\). A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using the E\ input as the data input and the select inputs (A0-A3) as addresses. This E\ input also serves as a chip select when these devices are cascaded.
When Latch Enable (LE\) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads. | -55 °C | 125 °C | Single Supply | 2 V | 6 V | Decoder/Demultiplexer | Surface Mount | 4:16 | 1 | 1 | 5.2 mA, 5.2 mA | 7.5 mm | 0.295 in | 24-SOIC | 24-SOIC | |||
-55 °C | 125 °C | Single Supply | 2 V | 6 V | Decoder/Demultiplexer | Through Hole | 4:16 | 1 | 1 | 5.2 mA, 5.2 mA | 24-DIP | 24-PDIP | 15.24 mm | 0.6 in | ||||
-55 °C | 125 °C | Single Supply | 2 V | 6 V | Decoder/Demultiplexer | Through Hole | 4:16 | 1 | 1 | 5.2 mA, 5.2 mA | 24-DIP | 24-PDIP | 0.3 in, 7.62 mm | |||||
-55 °C | 125 °C | Single Supply | 2 V | 6 V | Decoder/Demultiplexer | Through Hole | 4:16 | 1 | 1 | 5.2 mA, 5.2 mA | 24-DIP | 24-PDIP | 15.24 mm | 0.6 in |
Description
General part information
74HC4515 Series
The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4-to-16 line decoder. The selected output is enabled by a low on the enable input (E\). A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using the E\ input as the data input and the select inputs (A0-A3) as addresses. This E\ input also serves as a chip select when these devices are cascaded.
When Latch Enable (LE\) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads.
The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4-to-16 line decoder. The selected output is enabled by a low on the enable input (E\). A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using the E\ input as the data input and the select inputs (A0-A3) as addresses. This E\ input also serves as a chip select when these devices are cascaded.