CLVC573AQPWRG4Q1

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Texas Instruments

AUTOMOTIVE CATALOG OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsLVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)+27

CLVC573AQPWRG4Q1

Active

Texas Instruments

AUTOMOTIVE CATALOG OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsLVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)+27

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	CLVC573AQPWRG4Q1	SN74LVC573A-Q1 Series

Circuit	8:8	8:8
Current - Output High, Low [custom]	24 mA	24 mA
Current - Output High, Low [custom]	24 mA	24 mA
Delay Time - Propagation	1 ns	1 ns
Grade	Automotive	Automotive
Independent Circuits	1	1
Logic Type	D-Type Transparent Latch	D-Type Transparent Latch
Mounting Type	Surface Mount	Surface Mount
Operating Temperature [Max]	125 °C	125 °C
Operating Temperature [Min]	-40 °C	-40 °C
Output Type	Tri-State	Tri-State
Package / Case	0.173 in	0.173 - 7.5 mm
Package / Case	4.4 mm	4.4 mm
Package / Case	20-TSSOP	20-SOIC, 20-TSSOP
Qualification	AEC-Q100	AEC-Q100
Supplier Device Package	20-TSSOP	20-SOIC, 20-TSSOP
Voltage - Supply [Max]	3.6 V	3.6 V
Voltage - Supply [Min]	2 V	2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.87
		10	$ 0.78
		25	$ 0.74
		100	$ 0.61
		250	$ 0.57
		500	$ 0.50
		1000	$ 0.40
	Digi-Reel®	1	$ 0.87
		10	$ 0.78
		25	$ 0.74
		100	$ 0.61
		250	$ 0.57
		500	$ 0.50
		1000	$ 0.40
	Tape & Reel (TR)	2000	$ 0.33
Texas Instruments	LARGE T&R	1	$ 0.75
		100	$ 0.51
		250	$ 0.39
		1000	$ 0.26

SN74LVC573A-Q1 Series

Automotive Catalog Octal Transparent D-Type Latches With 3-State Outputs

Part	Mounting Type	Circuit	Voltage - Supply [Max]	Voltage - Supply [Min]	Grade	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Qualification	Package / Case	Package / Case	Delay Time - Propagation	Logic Type	Independent Circuits	Supplier Device Package	Output Type	Package / Case
Texas Instruments SN74LVC573AQDWRQ1	Surface Mount	8:8	3.6 V	2 V	Automotive	125 °C	-40 °C	24 mA	24 mA	AEC-Q100	0.295 in, 7.5 mm	20-SOIC	1 ns	D-Type Transparent Latch	1	20-SOIC	Tri-State
Texas Instruments CLVC573AQDWRG4Q1	Surface Mount	8:8	3.6 V	2 V	Automotive	125 °C	-40 °C	24 mA	24 mA	AEC-Q100	0.295 in, 7.5 mm	20-SOIC	1 ns	D-Type Transparent Latch	1	20-SOIC	Tri-State
Texas Instruments CLVC573AQPWRG4Q1	Surface Mount	8:8	3.6 V	2 V	Automotive	125 °C	-40 °C	24 mA	24 mA	AEC-Q100	0.173 in	20-TSSOP	1 ns	D-Type Transparent Latch	1	20-TSSOP	Tri-State	4.4 mm
Texas Instruments SN74LVC573AQPWRQ1	Surface Mount	8:8	3.6 V	2 V	Automotive	125 °C	-40 °C	24 mA	24 mA	AEC-Q100	0.173 in	20-TSSOP	1 ns	D-Type Transparent Latch	1	20-TSSOP	Tri-State	4.4 mm

Description

General part information

SN74LVC573A-Q1 Series

The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

Documents

Technical documentation and resources

CLVC573AQPWRG4Q1

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CLVC573AQPWRG4Q1

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Technical Specifications

Pricing

SN74LVC573A-Q1 Series

Description

SN74LVC573A-Q1 Series

Documents

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Design Summary for WCSP Little Logic (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Selecting the Right Level Translation Solution (Rev. A)

Low-Voltage Logic (LVC) Designer's Guide

Little Logic Guide 2018 (Rev. G)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Octal Transparent D-Type Latch With 3-State Outputs datasheet (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

Power-Up Behavior of Clocked Devices (Rev. B)

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

CMOS Power Consumption and CPD Calculation (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

LVC Characterization Information

Signal Switch Data Book (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Standard Linear & Logic for PCs, Servers & Motherboards

Texas Instruments Little Logic Application Report

Automotive Logic Devices Brochure

Live Insertion

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Logic Guide (Rev. AB)

Understanding Advanced Bus-Interface Products Design Guide

How to Select Little Logic (Rev. A)