CDCLVD110ARHBT
Active1-TO-10 LVDS CLOCK BUFFER UP TO 1100-MHZ WITH MINIMUM SKEW FOR CLOCK DISTRIBUTION
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CDCLVD110ARHBT
Active1-TO-10 LVDS CLOCK BUFFER UP TO 1100-MHZ WITH MINIMUM SKEW FOR CLOCK DISTRIBUTION
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CDCLVD110ARHBT | CDCLVD110A Series |
|---|---|---|
| Differential - Input:Output [custom] | True | True |
| Differential - Input:Output [custom] | True | True |
| Frequency - Max [Max] | 1.1 GHz | 1.1 GHz |
| Input | LVDS | LVDS |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Output | LVDS | LVDS |
| Package / Case | 32-VFQFN Exposed Pad | 32-LQFP, 32-VFQFN Exposed Pad |
| Ratio - Input:Output [custom] | 2 | 2 |
| Ratio - Input:Output [custom] | 10 | 10 |
| Supplier Device Package | 32-VQFN (5x5) | 32-LQFP (7x7), 32-VQFN (5x5) |
| Type | Multiplexer, Fanout Buffer (Distribution) | Multiplexer, Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 2.625 V | 2.625 V |
| Voltage - Supply [Min] | 2.375 V | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 13.88 | |
| 10 | $ 12.75 | |||
| 25 | $ 12.22 | |||
| 100 | $ 10.77 | |||
| Digi-Reel® | 1 | $ 13.88 | ||
| 10 | $ 12.75 | |||
| 25 | $ 12.22 | |||
| 100 | $ 10.77 | |||
| Tape & Reel (TR) | 250 | $ 10.24 | ||
| 500 | $ 9.58 | |||
| Texas Instruments | SMALL T&R | 1 | $ 10.86 | |
| 100 | $ 9.49 | |||
| 250 | $ 7.31 | |||
| 1000 | $ 6.54 | |||
CDCLVD110A Series
1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution
| Part | Package / Case | Type | Voltage - Supply [Min] | Voltage - Supply [Max] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Input | Number of Circuits | Output | Mounting Type | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Frequency - Max [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVD110AVF | 32-LQFP | Fanout Buffer (Distribution), Multiplexer | 2.375 V | 2.625 V | LVDS | 1 | LVDS | Surface Mount | -40 °C | 85 °C | 32-LQFP (7x7) | 2 | 10 | 1.1 GHz | ||
Texas Instruments CDCLVD110ARHBR | 32-VFQFN Exposed Pad | Fanout Buffer (Distribution), Multiplexer | 2.375 V | 2.625 V | LVDS | 1 | LVDS | Surface Mount | -40 °C | 85 °C | 32-VQFN (5x5) | 2 | 10 | 1.1 GHz | ||
Texas Instruments CDCLVD110ARHBT | 32-VFQFN Exposed Pad | Fanout Buffer (Distribution), Multiplexer | 2.375 V | 2.625 V | LVDS | 1 | LVDS | Surface Mount | -40 °C | 85 °C | 32-VQFN (5x5) | 2 | 10 | 1.1 GHz |
Description
General part information
CDCLVD110A Series
The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines.
When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled or disabled(3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.
The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems.
Documents
Technical documentation and resources