CDCLVD110A Series

1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution

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Catalog

1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution

Part	Package / Case	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Input	Number of Circuits	Output	Mounting Type	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Frequency - Max [Max]
Texas Instruments CDCLVD110AVF	32-LQFP	Fanout Buffer (Distribution), Multiplexer	2.375 V	2.625 V	LVDS	1	LVDS	Surface Mount	-40 °C	85 °C	32-LQFP (7x7)	2	10	1.1 GHz
Texas Instruments CDCLVD110ARHBR	32-VFQFN Exposed Pad	Fanout Buffer (Distribution), Multiplexer	2.375 V	2.625 V	LVDS	1	LVDS	Surface Mount	-40 °C	85 °C	32-VQFN (5x5)	2	10	1.1 GHz
Texas Instruments CDCLVD110ARHBT	32-VFQFN Exposed Pad	Fanout Buffer (Distribution), Multiplexer	2.375 V	2.625 V	LVDS	1	LVDS	Surface Mount	-40 °C	85 °C	32-VQFN (5x5)	2	10	1.1 GHz

Key Features

• Low-Output Skew <30 ps (Typical) for Clock-Distribution ApplicationsDistributes One Differential Clock Input to 10 LVDS Differential Clock OutputsVCCRange: 2.5 V ±5%Typical Signaling Rate Capability of Up to 1.1 GHzConfigurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0,CLK0or CLK1,CLK1InputsFull Rail-to-Rail Common-Mode Input RangeReceiver Input Threshold: ±100 mVAvailable in 32-Pin LQFP and VQFN PackageFail-Safe I/O-Pins for VDD= 0 V (Power Down)Low-Output Skew <30 ps (Typical) for Clock-Distribution ApplicationsDistributes One Differential Clock Input to 10 LVDS Differential Clock OutputsVCCRange: 2.5 V ±5%Typical Signaling Rate Capability of Up to 1.1 GHzConfigurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0,CLK0or CLK1,CLK1InputsFull Rail-to-Rail Common-Mode Input RangeReceiver Input Threshold: ±100 mVAvailable in 32-Pin LQFP and VQFN PackageFail-Safe I/O-Pins for VDD= 0 V (Power Down)

Description

The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled or disabled(3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled. The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems. The CDCLVD110A is characterized for operation from –40°C to 85°C. The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled or disabled(3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled. The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems. The CDCLVD110A is characterized for operation from –40°C to 85°C.