TPS7325QP
ActiveTexas Instruments
500-MA, 10-V, LOW-DROPOUT VOLTAGE REGULATOR WITH POWER GOOD & ENABLE
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TPS7325QP
ActiveTexas Instruments
500-MA, 10-V, LOW-DROPOUT VOLTAGE REGULATOR WITH POWER GOOD & ENABLE
Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | TPS7325QP | TPS73 Series |
|---|---|---|
| Control Features | Enable, Reset | Enable, Reset |
| Current - Output | 500 mA | 500 mA |
| Current - Supply (Max) [Max] | 550 µA | 550 µA |
| Mounting Type | Through Hole | Through Hole, Surface Mount |
| Number of Regulators | 1 | 1 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Output Configuration | Positive | Positive |
| Output Type | 27.03 °C/W | 27.03 °C/W |
| Output Type | - | Adjustable |
| Package / Case | 8-DIP | 8-DIP, 20-TSSOP, 8-SOIC |
| Package / Case | 0.3 in | 0.173 - 3.9 in |
| Package / Case | 7.62 mm | 4.4 - 7.62 mm |
| Protection Features | Over Temperature, Over Current, Short Circuit, Reverse Polarity | Over Temperature, Over Current, Short Circuit, Reverse Polarity, Under Voltage Lockout (UVLO) |
| PSRR | 53 dB | 53 - 68 dB |
| Supplier Device Package | 8-PDIP | 8-PDIP, 20-TSSOP, 8-SOIC |
| Voltage - Input (Max) [Max] | 10 V | 10 V |
| Voltage - Output (Max) | - | 9.75 V |
| Voltage - Output (Min/Fixed) | 2.5 V | 1.2 - 2.5 V |
| Voltage Dropout (Max) | 0.6 V | 0.5 - 0.6 V |
| Voltage Dropout (Max) | - | 0.21 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
TPS73 Series
500-mA, 10-V, low-dropout voltage regulator with power good & enable
| Part | Package / Case | Package / Case | Package / Case | Control Features | Voltage - Input (Max) [Max] | Voltage Dropout (Max) | Output Configuration | Current - Output | Operating Temperature [Max] | Operating Temperature [Min] | Protection Features | Mounting Type | Supplier Device Package | Output Type | Number of Regulators | Voltage - Output (Min/Fixed) | PSRR | Current - Supply (Max) [Max] | Voltage - Output (Max) [Max] | Output Type | Voltage Dropout (Max) [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments TPS7325QPThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 8-DIP | 0.3 in | 7.62 mm | Enable, Reset | 10 V | 0.6 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity, Short Circuit | Through Hole | 8-PDIP | 27.03 °C/W | 1 | 2.5 V | 53 dB | 550 µA | |||
Texas Instruments TPS7325QPWRThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 20-TSSOP | 0.173 in | 4.4 mm | Enable, Reset | 10 V | 0.6 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity, Short Circuit | Surface Mount | 20-TSSOP | 27.03 °C/W | 1 | 2.5 V | 53 dB | 550 µA | |||
Texas Instruments TPS7301QPThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 8-DIP | 0.3 in | 7.62 mm | Enable | 10 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO) | Through Hole | 8-PDIP | 1 | 1.2 V | 68 dB | 550 µA | 9.75 V | Adjustable | 0.21 V | ||
Texas Instruments TPS7301QDThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 8-SOIC | 3.9 mm | Enable | 10 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO) | Surface Mount | 8-SOIC | 1 | 1.2 V | 68 dB | 550 µA | 9.75 V | Adjustable | 0.21 V | |||
Texas Instruments TPS7330QDThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 8-SOIC | 3.9 mm | Enable, Reset | 10 V | 0.5 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity | Surface Mount | 8-SOIC | 27.03 °C/W | 1 | 53 dB | 550 µA | |||||
Texas Instruments TPS7325QDThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 8-SOIC | 3.9 mm | Enable, Reset | 10 V | 0.6 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity, Short Circuit | Surface Mount | 8-SOIC | 27.03 °C/W | 1 | 2.5 V | 53 dB | 550 µA | ||||
Texas Instruments TPS7330QPThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 8-DIP | 0.3 in | 7.62 mm | Enable, Reset | 10 V | 0.5 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity | Through Hole | 8-PDIP | 27.03 °C/W | 1 | 53 dB | 550 µA | ||||
Texas Instruments TPS7301QDRThe TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm.
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 uA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN\ (enable\) shuts down the regulator, reducing the quiescent current to 0.5 uA maximum at TJ= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2mm. | 8-SOIC | 3.9 mm | Enable | 10 V | Positive | 500 mA | 125 °C | -40 °C | Over Current, Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO) | Surface Mount | 8-SOIC | 1 | 1.2 V | 68 dB | 550 µA | 9.75 V | Adjustable | 0.21 V |
Description
General part information
TPS73 Series
The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.
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