ZL30681LFG7
Active1-CH SYNCE LINE CARD SYNCHRONIZER
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ZL30681LFG7
Active1-CH SYNCE LINE CARD SYNCHRONIZER
Technical Specifications
Parameters and characteristics for this part
| Specification | ZL30681LFG7 |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 1.045 GHz |
| Input | CMOS |
| Main Purpose | SONET/SDH, Wireless Base Stations, Ethernet |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 80-VFLGA |
| PLL | True |
| Ratio - Input:Output [custom] | 10 |
| Ratio - Input:Output [custom] | 5 |
| Supplier Device Package | 80-LGA (11x11) |
| Voltage - Supply | 1.8 V, 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 176 | $ 24.02 | |
| Microchip Direct | TRAY | 1 | $ 29.84 | |
| 25 | $ 24.88 | |||
| 100 | $ 22.62 | |||
| 1000 | $ 21.85 | |||
| 5000 | $ 21.58 | |||
ZL30681 Series
1-Ch SyncE Line Card Synchronizer
| Part | Voltage - Supply | Number of Circuits | Operating Temperature [Max] | Operating Temperature [Min] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Supplier Device Package | Mounting Type | PLL | Package / Case | Frequency - Max [Max] | Main Purpose | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Input |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology ZL30681LFG7 | 1.8 V, 3.3 V | 1 | 85 °C | -40 °C | 80-LGA (11x11) | Surface Mount | 80-VFLGA | 1.045 GHz | Ethernet, SONET/SDH, Wireless Base Stations | 10 | 5 | CMOS |
Description
General part information
ZL30681 Series
The ZL30681 offers one DPLL channel of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail.
Under the same family, the [ZL3067x](https://www.microchip.com/wwwproducts/en/ZL30673)offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for timing card interface. Also available is [ZL3077x](https://www.microchip.com/wwwproducts/en/ZL30773)that support one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms.
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Documents
Technical documentation and resources