Catalog
1-Ch SyncE Line Card Synchronizer
Key Features
• Key Features* One independent DPLL channel
• * Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
• * Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
• * Split oscillator option lowers cost, lowers jitter, and provides redundancy
• * Excellent jitter performance of <300 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
• * Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz
• * One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
• * 8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs
• * Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
• * Up to three programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
• * Accepts up to 10 differential or 10 single ended input references
• * Full reference monitoring of electrical failures
• * Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
• * Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
• * Easy Configuration and dynamic programming via SPI/I2C interface
• * Factory programming available
• * Operates from a single crystal resonator or clock oscillator
Description
AI
The ZL30681 offers one DPLL channel of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail.
Under the same family, the [ZL3067x](https://www.microchip.com/wwwproducts/en/ZL30673)offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for timing card interface. Also available is [ZL3077x](https://www.microchip.com/wwwproducts/en/ZL30773)that support one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms.
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AN3467 Crystals and Oscillators for Next Generation Timing Solutions
ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices
ZLAN-656 Redwood PSNR
ZLAN-664 Board Design Recommendations for Redwood
ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood
ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package
ZLAN-724 Phase Measurement Compensation for Redwood
ZLAN-728 Indirect Read and Write Procedure