SN74AS175BN
ActiveQUADRUPLE D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR
SN74AS175BN
ActiveQUADRUPLE D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR
Description
General part information
74AS175 Series
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AS175BN |
|---|---|
| Clock Frequency | 100 MHz |
| Current - Output High | 2 mA |
| Current - Output Low | 20 mA |
| Current - Quiescent (Iq) | 34 mA |
| Function | Master Reset |
| Max CL | 50 pF |
| Max Propagation Delay | 10 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 4 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 70 °C |
| Operating Temperature (Min) | 0 °C |
| Output Type | Complementary |
| Package Length | 0.3 in |
| Package Name | 16-DIP, 16-PDIP |
| Package Width | 7.62 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply (Maximum) | 5.5 V |
| Voltage - Supply (Minimum) | 4.5 V |
Pricing
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