Zenode.ai Logo
Log InSign Up
SN74HC166DR - 16 SOIC

SN74HC166DR

Active
Texas Instruments

8-BIT PARALLEL-LOAD SHIFT REGISTERS 16-SOIC -40 TO 85

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsDatasheetDatasheet+15
SN74HC166DR - 16 SOIC

SN74HC166DR

Active
Texas Instruments

8-BIT PARALLEL-LOAD SHIFT REGISTERS 16-SOIC -40 TO 85

Deep-Dive with AI

DocumentsDatasheetDatasheet+15

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationSN74HC166DR74HC166 Series
FunctionParallel or Serial to SerialParallel or Serial to Serial
Grade-Automotive
Logic TypeShift RegisterShift Register
Mounting TypeSurface MountSurface Mount, Through Hole
Number of Bits per Element88
Number of Elements [custom]11
Operating Temperature [Max]85 °C85 - 125 °C
Operating Temperature [Min]-40 °C-55 - -40 °C
Output TypePush-PullPush-Pull
Package / Case16-SOIC16-TSSOP, 16-DIP, 16-SOIC, 16-SSOP, 16-SOIC (0.209", 5.30mm Width)
Package / Case3.9 mm Width, 0.154 in0.154 - 7.62 in
Package / Case-0.173 "
Package / Case-4.4 mm
Package / Case-0.209 in
Package / Case-5.3 mm
Qualification-AEC-Q100
Supplier Device Package16-SOIC16-TSSOP, 16-PDIP, 16-SOIC, 16-SSOP, 16-SO
Voltage - Supply [Max]6 V6 V
Voltage - Supply [Min]2 V2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

74HC166 Series

8-Bit Parallel-Load Shift Registers

PartNumber of Bits per ElementVoltage - Supply [Min]Voltage - Supply [Max]FunctionNumber of Elements [custom]Supplier Device PackageLogic TypeMounting TypeOutput TypePackage / Case [x]Package / CasePackage / Case [x]Operating Temperature [Min]Operating Temperature [Max]Package / CasePackage / Case [y]Package / Case [y]QualificationGrade
Texas Instruments
SN74HC166PWG4
Shift Shift Register 1 Element 8 Bit 16-TSSOP
8
2 V
6 V
Parallel or Serial to Serial
1
16-TSSOP
Shift Register
Surface Mount
Push-Pull
0.173 "
16-TSSOP
4.4 mm
-40 °C
85 °C
Texas Instruments
SN74HC166N
Shift Shift Register 1 Element 8 Bit 16-PDIP
8
2 V
6 V
Parallel or Serial to Serial
1
16-PDIP
Shift Register
Through Hole
Push-Pull
16-DIP
-40 °C
85 °C
0.3 in, 7.62 mm
Texas Instruments
CD74HC166M96
Shift Shift Register 1 Element 8 Bit 16-SOIC
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-55 °C
125 °C
0.154 in, 3.9 mm Width
Texas Instruments
SN74HC166DR
Shift Shift Register 1 Element 8 Bit 16-SOIC
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-40 °C
85 °C
0.154 in, 3.9 mm Width
Texas Instruments
SN74HC166DRE4
Shift Shift Register 1 Element 8 Bit 16-SOIC
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-40 °C
85 °C
0.154 in, 3.9 mm Width
Texas Instruments
SN74HC166PWR
Shift Shift Register 1 Element 8 Bit 16-TSSOP
8
2 V
6 V
Parallel or Serial to Serial
1
16-TSSOP
Shift Register
Surface Mount
Push-Pull
0.173 "
16-TSSOP
4.4 mm
-40 °C
85 °C
Texas Instruments
CD74HC166MG4
Shift Shift Register 1 Element 8 Bit 16-SOIC
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-55 °C
125 °C
0.154 in, 3.9 mm Width
Texas Instruments
SN74HC166DBR
Shift Shift Register 1 Element 8 Bit 16-SSOP
8
2 V
6 V
Parallel or Serial to Serial
1
16-SSOP
Shift Register
Surface Mount
Push-Pull
16-SSOP
-40 °C
85 °C
0.209 in
5.3 mm
Texas Instruments
SN74HC166PW
Shift Shift Register 1 Element 8 Bit 16-TSSOP
8
2 V
6 V
Parallel or Serial to Serial
1
16-TSSOP
Shift Register
Surface Mount
Push-Pull
0.173 "
16-TSSOP
4.4 mm
-40 °C
85 °C
Texas Instruments
SN74HC166AIPWRG4Q1
This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LDenables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.CLRoverrides all other inputs, including CLK, and resets all flip-flops to zero. This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LDenables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.CLRoverrides all other inputs, including CLK, and resets all flip-flops to zero.
8
2 V
6 V
Parallel or Serial to Serial
1
16-TSSOP
Shift Register
Surface Mount
Push-Pull
0.173 "
16-TSSOP
4.4 mm
-40 °C
85 °C
AEC-Q100
Automotive
Texas Instruments
SN74HC166NS
Shift Shift Register 1 Element 8 Bit 16-SO
8
2 V
6 V
Parallel or Serial to Serial
1
16-SO
Shift Register
Surface Mount
Push-Pull
16-SOIC (0.209", 5.30mm Width)
-40 °C
85 °C
Texas Instruments
SN74HC166PWT
Shift Shift Register 1 Element 8 Bit 16-TSSOP
8
2 V
6 V
Parallel or Serial to Serial
1
16-TSSOP
Shift Register
Surface Mount
Push-Pull
0.173 "
16-TSSOP
4.4 mm
-40 °C
85 °C
Texas Instruments
CD74HC166MT
Shift Shift Register 1 Element 8 Bit 16-SOIC
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-55 °C
125 °C
0.154 in, 3.9 mm Width
Texas Instruments
CD74HC166M
Shift Shift Register 1 Element 8 Bit 16-SOIC
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-55 °C
125 °C
0.154 in, 3.9 mm Width
Texas Instruments
SN74HC166AIDRQ1
This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LDenables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.CLRoverrides all other inputs, including CLK, and resets all flip-flops to zero. This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LDenables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.CLRoverrides all other inputs, including CLK, and resets all flip-flops to zero.
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-40 °C
85 °C
0.154 in, 3.9 mm Width
AEC-Q100
Automotive
Texas Instruments
SN74HC166AIPWRQ1
Shift Shift Register 1 Element 8 Bit 16-TSSOP
8
2 V
6 V
Parallel or Serial to Serial
1
16-TSSOP
Shift Register
Surface Mount
Push-Pull
0.173 "
16-TSSOP
4.4 mm
-40 °C
85 °C
AEC-Q100
Automotive
Texas Instruments
SN74HC166D
Shift Shift Register 1 Element 8 Bit 16-SOIC
8
2 V
6 V
Parallel or Serial to Serial
1
16-SOIC
Shift Register
Surface Mount
Push-Pull
16-SOIC
-40 °C
85 °C
0.154 in, 3.9 mm Width
Texas Instruments
SN74HC166NSR
Shift Shift Register 1 Element 8 Bit 16-SO
8
2 V
6 V
Parallel or Serial to Serial
1
16-SO
Shift Register
Surface Mount
Push-Pull
16-SOIC (0.209", 5.30mm Width)
-40 °C
85 °C

Description

General part information

74HC166 Series

8-Bit Parallel-Load Shift Registers