
CDCLVD2104RHDR
ActiveLOW JITTER, DUAL 1:4 UNIVERSAL-TO-LVDS BUFFER

CDCLVD2104RHDR
ActiveLOW JITTER, DUAL 1:4 UNIVERSAL-TO-LVDS BUFFER
Description
General part information
CDCLVD2104 Series
The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2104 is specifically designed for driving 50-transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
Technical Specifications
Parameters and characteristics for this part
| Specification | CDCLVD2104RHDR |
|---|---|
| Differential Input | Yes |
| Differential Output | Yes |
| Frequency - Max | 800 MHz |
| Input | LVPECL, LVDS, LVCMOS |
| Input Ratio | 1 |
| Mounting Type | Surface Mount |
| Number of Circuits | 2 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output | LVDS |
| Output Ratio | 4 |
| Package / Case | 28-VFQFN Exposed Pad |
| Package Length | 5 mm |
| Package Name | 28-VQFN |
| Package Width | 5 mm |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply (Maximum) | 2.625 V |
| Voltage - Supply (Minimum) | 2.375 V |
Pricing
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