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ZL30169LDG1 - VQFN / 32

ZL30169LDG1

Active
Microchip Technology

3-INPUT, 3-OUTPUT CLOCK TRANSLATOR FOR OTN 32 VQFN 5X5X1MM TRAY ROHS COMPLIANT: YES

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ZL30169LDG1 - VQFN / 32

ZL30169LDG1

Active
Microchip Technology

3-INPUT, 3-OUTPUT CLOCK TRANSLATOR FOR OTN 32 VQFN 5X5X1MM TRAY ROHS COMPLIANT: YES

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationZL30169LDG1ZL30169 Series
--
Differential - Input:Output [custom]TrueTrue
Differential - Input:Output [custom]TrueTrue
Frequency - Max [Max]1.035 GHz1.035 GHz
InputCrystal, CMOS, CMLCrystal, CMOS, CML
Main PurposeTelecomTelecom
Mounting TypeSurface MountSurface Mount
Number of Circuits11
Operating Temperature [Max]85 °C85 °C
Operating Temperature [Min]-40 °C-40 °C
OutputCMOS, CMLCMOS, CML
PLLTrueTrue
Ratio - Input:Output4:34:3
Supplier Device Package32-QFN (5x5)32-QFN (5x5)

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 20.58
25$ 17.14
100$ 16.57
Microchip DirectTRAY 1$ 20.58
25$ 17.14
100$ 15.59
1000$ 14.40
5000$ 13.66
NewarkEach 100$ 15.59

ZL30169 Series

1-Ch Low Cost OTN Jitter Attenuator

PartOperating Temperature [Max]Operating Temperature [Min]OutputSupplier Device PackagePLLRatio - Input:OutputDifferential - Input:Output [custom]Differential - Input:Output [custom]InputMounting TypeFrequency - Max [Max]Number of CircuitsMain Purpose
Microchip Technology
ZL30169LDF1
Microchip Technology
ZL30169LDG1
Microchip Technology
ZL30169LDG1
85 °C
-40 °C
CML, CMOS
32-QFN (5x5)
4:3
CML, CMOS, Crystal
Surface Mount
1.035 GHz
1
Telecom

Description

General part information

ZL30169 Series

[CREATE AND SAMPLE YOUR CUSTOM ZL30169 HERE](https://clockworks.microchip.com/microchip/design/inputZL)

The ZL30169 is a high performance OTN clock translator that provides output clocks with jitter performance of 250fs RMS. The device integrates a digital phase locked loop (DPLL), analog PLL and EEPROM into a tiny 5x5mm 32 pin QFN package. With programmable loop bandwidth from 14Hz to 500 Hz the DPLL provides hitless reference switching, holdover and jitter filtering. The integrated APLL generates the ultra-low jitter output clocks programmable to any frequency from <1Hz to 1035MHz. The integrated EEPROM provides automatic self-configuration of the device at start-up.