CD54HC194F3A
ActiveHIGH SPEED CMOS LOGIC 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
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CD54HC194F3A
ActiveHIGH SPEED CMOS LOGIC 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC194F3A |
|---|---|
| Function | Universal |
| Logic Type | Register, Bidirectional |
| Mounting Type | Through Hole |
| Number of Bits per Element | 4 |
| Number of Elements [custom] | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 C |
| Output Type | Push-Pull |
| Package / Case | 16-CDIP (0.300", 7.62mm) |
| Supplier Device Package | 16-CDIP |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
CD54HC194 Series
High Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
| Part | Mounting Type | Supplier Device Package | Function | Package / Case | Voltage - Supply [Min] | Voltage - Supply [Max] | Operating Temperature [Min] | Operating Temperature [Max] | Logic Type | Number of Bits per Element | Number of Elements [custom] | Output Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HC194F3AThe ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.
The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin. | Through Hole | 16-CDIP | Universal | 16-CDIP (0.300", 7.62mm) | 2 V | 6 V | -55 C | 125 °C | Register, Bidirectional | 4 | 1 | Push-Pull |
Description
General part information
CD54HC194 Series
The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.
The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.
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