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TMS320C6655SCZH

TMS320C6655SCZH

Obsolete
Texas Instruments

HIGH PERFORMANCE SINGLE-CORE C66X FIXED AND FLOATING-POINT DSP- UP TO 1.25GHZ

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TMS320C6655SCZH

TMS320C6655SCZH

Obsolete
Texas Instruments

HIGH PERFORMANCE SINGLE-CORE C66X FIXED AND FLOATING-POINT DSP- UP TO 1.25GHZ

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Description

General part information

TMS320 Series

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

Technical Specifications

Parameters and characteristics for this part

SpecificationTMS320C6655SCZH
Clock Rate (Frequency)1 GHz
InterfaceUART, PCIe, DDR3, I2C, SPI, EBI/EMI, McBSP, Ethernet, UPP
Mounting TypeSurface Mount
Non-Volatile Memory Size128 kB
Non-Volatile Memory TypeROM
On-Chip RAM2.06 MB
Operating Temperature (Max)85 °C
Operating Temperature (Min)0 °C
Package / CaseFCBGA, 625-BFBGA
Package Length21 mm
Package Name625-FCBGA
Package Width21 mm
TypeFixed/Floating Point
Voltage - Core1 V
Voltage - I/O (Option 1)1 V
Voltage - I/O (Option 2)1.5 V
Voltage - I/O (Option 3)1.8 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)
PCIe Use Cases for KeyStone Devices
C66x DSP Cache User's Guide
Clocking Design Guide for KeyStone Devices
TI Keystone DSP PCIe SerDes IBIS-AMI Models
Software-Based Ultrasound Beamforming on Multicore DSPs
TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A)
KeyStone Lab Manual - Training
Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A)
TMS320C66x high-performance multicore DSPs for video surveillance
Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide
How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)
Accelerating high-performance computing development with Desktop Linux SDK
Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)
Plastic Ball Grid Array [PBGA] Application Note (Rev. B)
TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)
Flip Chip Ball Grid Array Package Reference Guide (Rev. A)
Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)
Optimizing Loops on the C66x DSP
HyperLink for KeyStone Devices User's Guide (Rev. C)
TI’s processors leading the way in embedded analytics
64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)
KeyStone I DDR3 Initialization (Rev. E)
Maximizing Multicore Efficiency with Navigator Runtime
KeyStone I DDR3 interface bring-up
System Analyzer User's Guide (Rev. F)
Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)
PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)
TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. D)
TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG
Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)
General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide
Keystone Bootloader Resources and FAQ
External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)
Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)
SERDES Link Commissioning on KeyStone I and II Devices
Debug and Trace for KeyStone I Devices User's Guide (Rev. A)
Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide
Universal Parallel Port (uPP) for KeyStone Architecture User's Guide
Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices
Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)
SerDes Implementation Guidelines for KeyStone I Devices
Keystone Error Detection and Correction EDC ECC (Rev. A)
TMS320C66x DSP Generation of Devices (Rev. A)
Superior performance at breakthrough size, weight & power
Keystone Multicore Device Family Schematic Checklist
Leveraging multicore processors for machine vision applications
DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)
Software and Hardware Design Challenges Due to Dynamic Raw NAND Market
Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP
AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)
TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C)
Multicore Programming Guide (Rev. B)
TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
Ethernet Media Access Controller (EMAC) User's Guide for KeyStone Devices
TI DSP Benchmarking
KeyStone Memory Architecture White Paper (Rev. A)
OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A)
Hardware Design Guide for KeyStone Devices (Rev. D)
DDR3 Design Requirements for KeyStone Devices (Rev. D)
SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)
C66x CPU and Instruction Set Reference Guide
DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E)
Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)
Using DSPLIB FFT Implementation for Real Input and Without Data Scaling
Thermal Design Guide for DSP and Arm Application Processors (Rev. B)
C66x CorePac User's Guide (Rev. C)
Introduction to TMS320C6000 DSP Optimization
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A)
KeyStone Multicore SoC Tool Suite: one platform for all needs
TMS320C6655SCZH | Datasheet