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FCBGA (CZH)

TMS320C6655CZH25

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Texas Instruments

HIGH PERFORMANCE SINGLE-CORE C66X FIXED AND FLOATING-POINT DSP- UP TO 1.25GHZ

FCBGA (CZH)

TMS320C6655CZH25

Active

Texas Instruments

HIGH PERFORMANCE SINGLE-CORE C66X FIXED AND FLOATING-POINT DSP- UP TO 1.25GHZ

Description Specifications Series Pricing CAD Documents

Description

General part information

TMS320 Series

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

Technical Specifications

Parameters and characteristics for this part

Specification	TMS320C6655CZH25

Clock Rate (Frequency)	1.25 GHz
Interface	UART, PCIe, DDR3, I2C, SPI, EBI/EMI, McBSP, Ethernet, UPP
Mounting Type	Surface Mount
Non-Volatile Memory Size	128 kB
Non-Volatile Memory Type	ROM
On-Chip RAM	2.06 MB
Operating Temperature (Max)	85 °C
Operating Temperature (Min)	0 °C
Package / Case	FCBGA, 625-BFBGA
Package Length	21 mm
Package Name	625-FCBGA
Package Width	21 mm
Type	Fixed/Floating Point
Voltage - Core	1 V
Voltage - I/O (Option 1)	1 V
Voltage - I/O (Option 2)	1.5 V
Voltage - I/O (Option 3)	1.8 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)

Flip Chip Ball Grid Array Package Reference Guide (Rev. A)

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

Hardware Design Guide for KeyStone Devices (Rev. D)

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide

Keystone Multicore Device Family Schematic Checklist

TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C)

HyperLink for KeyStone Devices User's Guide (Rev. C)

SerDes Implementation Guidelines for KeyStone I Devices

TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)

DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E)

Software-Based Ultrasound Beamforming on Multicore DSPs

TI DSP Benchmarking

Introduction to TMS320C6000 DSP Optimization

TMS320C66x high-performance multicore DSPs for video surveillance

TI’s processors leading the way in embedded analytics

OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A)

Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices

Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A)

KeyStone I DDR3 interface bring-up

Accelerating high-performance computing development with Desktop Linux SDK

TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A)

Superior performance at breakthrough size, weight & power

Keystone Error Detection and Correction EDC ECC (Rev. A)

Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)

Ethernet Media Access Controller (EMAC) User's Guide for KeyStone Devices

TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)

Plastic Ball Grid Array [PBGA] Application Note (Rev. B)

Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP

KeyStone Multicore SoC Tool Suite: one platform for all needs

TI Keystone DSP Hyperlink SerDes IBIS-AMI Models

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

Debug and Trace for KeyStone I Devices User's Guide (Rev. A)

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

C66x CPU and Instruction Set Reference Guide

SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)

KeyStone I DDR3 Initialization (Rev. E)

Using DSPLIB FFT Implementation for Real Input and Without Data Scaling

DDR3 Design Requirements for KeyStone Devices (Rev. D)

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

PCIe Use Cases for KeyStone Devices

TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. D)

KeyStone Memory Architecture White Paper (Rev. A)

External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)

AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)

Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A)

Maximizing Multicore Efficiency with Navigator Runtime

Leveraging multicore processors for machine vision applications

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

Optimizing Loops on the C66x DSP

System Analyzer User's Guide (Rev. F)

Universal Parallel Port (uPP) for KeyStone Architecture User's Guide

Multicore Programming Guide (Rev. B)

TMS320C66x DSP Generation of Devices (Rev. A)

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

Software and Hardware Design Challenges Due to Dynamic Raw NAND Market

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

C66x CorePac User's Guide (Rev. C)

C66x DSP Cache User's Guide

TI Keystone DSP PCIe SerDes IBIS-AMI Models

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG

Clocking Design Guide for KeyStone Devices

Keystone Bootloader Resources and FAQ

DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

SERDES Link Commissioning on KeyStone I and II Devices

KeyStone Lab Manual - Training

PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)

TMS320 Series

C2000™ Enhanced Product 32-bit MCU with 800 MIPS, 2xCPU, 2xCLA, FPU, TMU, 1 MB flash, EMIF, 16b ADC

...

Part	Program Memory Size	Program Memory Width	Program Memory Depth	Peripherals	A/D Resolution (bits)	A/D Channels	Mounting Type	Number of I/O	RAM Size Width	RAM Size Depth	Package Width	Package Name	Package Length	Program Memory Type	Voltage - Supply (Vcc/Vdd) Maximum	Voltage - Supply (Vcc/Vdd) Minimum	Package / Case	Core Size (Bit Width)	Operating Temperature (Max)	Operating Temperature (Min)	Connectivity	Core Processor	Oscillator Type	Speed
Texas Instruments TMS320F28062UPZT	128 KB	16	64 K	Brown-out Detect DMA POR PWM Reset WDT	12 bit	16 count	Surface Mount	54	16 bit	26 K	14 mm	100-LQFP	14 mm	FLASH	1.995 V	1.71 V	100-LQFP	32 Bit	105 °C	-40 °C	CANbus I2C McBSP SCI SPI UART USART USB	C28x	Internal	90 MHz

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