CDCLVP2106EVM
ActiveEVAL MODULE FOR CDCLVP2106
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CDCLVP2106EVM
ActiveEVAL MODULE FOR CDCLVP2106
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CDCLVP2106EVM | CDCLVP2106 Series |
|---|---|---|
| Differential - Input:Output | - | True |
| Differential - Input:Output | - | True |
| Embedded | False | False |
| Frequency - Max | - | 2 GHz |
| Function | Clock Buffer | Clock Buffer |
| Input | - | LVCMOS, LVTTL, LVPECL, LVDS |
| Mounting Type | - | Surface Mount |
| Number of Circuits | - | 2 |
| Operating Temperature | - | -40 °C |
| Operating Temperature | - | 85 °C |
| Output | - | LVPECL |
| Package / Case | - | 40-VFQFN Exposed Pad |
| Ratio - Input:Output | - | 12 |
| Ratio - Input:Output | - | 1 |
| Supplied Contents | Board(s) | Board(s) |
| Supplier Device Package | - | 40-VQFN (6x6) |
| Type | Timing | Fanout Buffer (Distribution), Timing |
| Voltage - Supply | - | 2.375 V |
| Voltage - Supply | - | 3.6 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Box | 1 | $ 178.80 | |
CDCLVP2106 Series
Low jitter, dual 1:6 universal-to-LVPECL buffer
| Part | Type | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Frequency - Max [Max] | Number of Circuits | Package / Case | Output | Input | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] | Mounting Type | Voltage - Supply [Min] | Voltage - Supply [Max] | Supplied Contents | Embedded | Function |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVP2106RHAT | Fanout Buffer (Distribution) | 2 GHz | 2 | 40-VFQFN Exposed Pad | LVPECL | LVCMOS, LVDS, LVPECL, LVTTL | 12 | 1 | 40-VQFN (6x6) | -40 °C | 85 °C | Surface Mount | 2.375 V | 3.6 V | |||||
Texas Instruments CDCLVP2106EVM | Timing | Board(s) | Clock Buffer |
Description
General part information
CDCLVP2106 Series
The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
Documents
Technical documentation and resources