CDCLVP2106 Series

Low jitter, dual 1:6 universal-to-LVPECL buffer

Link to Manufacturer Page: https://www.ti.com/

Catalog

Low jitter, dual 1:6 universal-to-LVPECL buffer

Part	Type	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Frequency - Max [Max]	Number of Circuits	Package / Case	Output	Input	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Supplier Device Package	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplied Contents	Embedded	Function
Texas Instruments CDCLVP2106RHAT	Fanout Buffer (Distribution)			2 GHz	2	40-VFQFN Exposed Pad	LVPECL	LVCMOS, LVDS, LVPECL, LVTTL	12	1	40-VQFN (6x6)	-40 °C	85 °C	Surface Mount	2.375 V	3.6 V
Texas Instruments CDCLVP2106EVM	Timing																Board(s)		Clock Buffer

Key Features

• Dual 1:6 Differential BufferTwo Clock InputsUniversal Inputs Can Accept LVPECL, LVDS,LVCMOS/LVTTL12 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 92 mAVery Low Additive Jitter: <100 fs,RMS in 10-kHz to 20-MHz Offset Range2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Within Bank Output Skew: 20 psLVPECL Reference Voltage, VAC_REF,Available for Capacitive-Coupled InputsIndustrial Temperature Range: –40°Cto +85°CSupports 105°C PCB Temperature (Measuredwith a Thermal Pad)Available in 6-mm × 6-mm, 40-Pin VQFN(RHA) PackageESD Protection Exceeds 2000 V (HBM)Dual 1:6 Differential BufferTwo Clock InputsUniversal Inputs Can Accept LVPECL, LVDS,LVCMOS/LVTTL12 LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 92 mAVery Low Additive Jitter: <100 fs,RMS in 10-kHz to 20-MHz Offset Range2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 550 psMaximum Within Bank Output Skew: 20 psLVPECL Reference Voltage, VAC_REF,Available for Capacitive-Coupled InputsIndustrial Temperature Range: –40°Cto +85°CSupports 105°C PCB Temperature (Measuredwith a Thermal Pad)Available in 6-mm × 6-mm, 40-Pin VQFN(RHA) PackageESD Protection Exceeds 2000 V (HBM)

Description

The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications. The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL. The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package. The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications. The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL. The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.