CD54HC4017F3A
ActiveHIGH SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS
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CD54HC4017F3A
ActiveHIGH SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC4017F3A |
|---|---|
| Count Rate | 35 MHz |
| Direction | Up |
| Logic Type | Decade, Counter |
| Mounting Type | Through Hole |
| Number of Bits per Element | 10 |
| Number of Elements [custom] | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 C |
| Package / Case | 16-CDIP (0.300", 7.62mm) |
| Reset | Asynchronous |
| Supplier Device Package | 16-CDIP |
| Timing | Synchronous |
| Trigger Type | Negative, Positive |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
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CD54HC4017 Series
High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
| Part | Timing | Supplier Device Package | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] | Trigger Type | Reset | Number of Elements [custom] | Logic Type | Mounting Type | Count Rate | Direction | Number of Bits per Element | Operating Temperature [Min] | Operating Temperature [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HC4017F3AThe CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.
The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C. | Synchronous | 16-CDIP | 16-CDIP (0.300", 7.62mm) | 6 V | 2 V | Negative, Positive | Asynchronous | 1 | Counter, Decade | Through Hole | 35 MHz | Up | 10 | -55 C | 125 °C |
Description
General part information
CD54HC4017 Series
The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.
The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.
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