SN74ABT162601DGG
ObsoleteIC UNIV BUS TXRX 18BIT 56TSSOP
SN74ABT162601DGG
ObsoleteIC UNIV BUS TXRX 18BIT 56TSSOP
Description
General part information
74ABT162601 Series
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB\ is active-low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ABT162601DGG |
|---|---|
| Current - Output High (Max) | 64 mA |
| Current - Output High (Min) | 32 mA |
| Current - Output Low (Max) | 12 mA |
| Current - Output Low (Min) | 12 mA |
| Logic Type | Universal Bus Transceiver |
| Mounting Type | Surface Mount |
| Number of Circuits (Bit) | 18 Bit |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Package Length | 0.24 in |
| Package Name | 56-TFSOP, 56-TSSOP |
| Package Width | 6.1 mm |
| Voltage - Supply (Maximum) | 5.5 V |
| Voltage - Supply (Minimum) | 4.5 V |
Pricing
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