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CD74HC75M96 - https://ti.com/content/dam/ticom/images/products/package/d/d0016a.png

CD74HC75M96

Active
Texas Instruments

HIGH SPEED CMOS LOGIC DUAL 2-BIT BISTABLE TRANSPARENT LATCHES

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Search across all available documentation for this part.

DocumentsCD54HC75, CD74HC75, CD54HCT75, CD74HCT75 datasheet (Rev. F)
CD74HC75M96 - https://ti.com/content/dam/ticom/images/products/package/d/d0016a.png

CD74HC75M96

Active
Texas Instruments

HIGH SPEED CMOS LOGIC DUAL 2-BIT BISTABLE TRANSPARENT LATCHES

Deep-Dive with AI

DocumentsCD54HC75, CD74HC75, CD54HCT75, CD74HCT75 datasheet (Rev. F)

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationCD74HC75M96CD74HC75 Series
Circuit2:22:2
Current - Output High, Low5.2 mA, 5.2 mA5.2 mA
Delay Time - Propagation10 ns10 ns
Independent Circuits22
Logic TypeD-Type Transparent LatchD-Type Transparent Latch
Mounting TypeSurface MountSurface Mount, Through Hole
Operating Temperature [Max]125 °C125 °C
Operating Temperature [Min]-55 °C-55 °C
Output TypeDifferentialDifferential
Package / Case16-SOIC16-SOIC, 16-TSSOP, 16-DIP
Package / Case3.9 mm Width, 0.154 in0.154 - 7.62 mm Width
Package / Case-0.173 "
Package / Case-4.4 mm
Supplier Device Package16-SOIC16-SOIC, 16-TSSOP, 16-PDIP
Voltage - Supply [Max]6 V6 V
Voltage - Supply [Min]2 V2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

CD74HC75 Series

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latches

PartCurrent - Output High, LowMounting TypeLogic TypeOutput TypeVoltage - Supply [Min]Voltage - Supply [Max]Independent CircuitsCircuitSupplier Device PackageDelay Time - PropagationPackage / CasePackage / CaseOperating Temperature [Min]Operating Temperature [Max]Package / Case [x]Package / Case [x]
Texas Instruments
CD74HC75M96
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected. The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
5.2 mA, 5.2 mA
Surface Mount
D-Type Transparent Latch
Differential
2 V
6 V
2
2:2
16-SOIC
10 ns
16-SOIC
0.154 in, 3.9 mm Width
-55 °C
125 °C
Texas Instruments
CD74HC75PWT
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected. The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
5.2 mA, 5.2 mA
Surface Mount
D-Type Transparent Latch
Differential
2 V
6 V
2
2:2
16-TSSOP
10 ns
16-TSSOP
-55 °C
125 °C
0.173 "
4.4 mm
Texas Instruments
CD74HC75MT
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected. The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
5.2 mA, 5.2 mA
Surface Mount
D-Type Transparent Latch
Differential
2 V
6 V
2
2:2
16-SOIC
10 ns
16-SOIC
0.154 in, 3.9 mm Width
-55 °C
125 °C
Texas Instruments
CD74HC75E
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected. The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
5.2 mA, 5.2 mA
Through Hole
D-Type Transparent Latch
Differential
2 V
6 V
2
2:2
16-PDIP
10 ns
16-DIP
0.3 in, 7.62 mm
-55 °C
125 °C
Texas Instruments
CD74HC75PWR
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected. The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
5.2 mA, 5.2 mA
Surface Mount
D-Type Transparent Latch
Differential
2 V
6 V
2
2:2
16-TSSOP
10 ns
16-TSSOP
-55 °C
125 °C
0.173 "
4.4 mm
Texas Instruments
CD74HC75M
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected. The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
5.2 mA, 5.2 mA
Surface Mount
D-Type Transparent Latch
Differential
2 V
6 V
2
2:2
16-SOIC
10 ns
16-SOIC
0.154 in, 3.9 mm Width
-55 °C
125 °C
Texas Instruments
CD74HC75PW
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected. The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
5.2 mA, 5.2 mA
Surface Mount
D-Type Transparent Latch
Differential
2 V
6 V
2
2:2
16-TSSOP
10 ns
16-TSSOP
-55 °C
125 °C
0.173 "
4.4 mm

Description

General part information

CD74HC75 Series

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.

Documents

Technical documentation and resources

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 datasheet (Rev. F)

Data sheet