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TC8020K6-G - 56-QFN

TC8020K6-G

Active
Microchip Technology

SIX PAIR, N- AND P-CHANNEL ENHANCEMENT-MODE MOSFET 56 VQFN 8X8X1.0MM TRAY ROHS COMPLIANT: YES

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TC8020K6-G - 56-QFN

TC8020K6-G

Active
Microchip Technology

SIX PAIR, N- AND P-CHANNEL ENHANCEMENT-MODE MOSFET 56 VQFN 8X8X1.0MM TRAY ROHS COMPLIANT: YES

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Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationTC8020K6-GTC8020 Series
Configuration-6
Configuration-6
Drain to Source Voltage (Vdss)-200 V
Input Capacitance (Ciss) (Max) @ Vds-50 pF
Mounting Type-Surface Mount
null-
Operating Temperature--55 °C
Operating Temperature-150 °C
Package / Case-56-VFQFN Exposed Pad
Rds On (Max) @ Id, Vgs-8 Ohm
Supplier Device Package-56-QFN (8x8)
Technology-MOSFET (Metal Oxide)
Vgs(th) (Max) @ Id-2.4 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 10.98
25$ 9.14
100$ 8.33
Microchip DirectTRAY 1$ 10.98
25$ 9.14
100$ 8.33
1000$ 8.05
5000$ 7.95
NewarkEach 100$ 8.58

TC8020 Series

Six Pair, N/P Channel Enhancement-Mode MOSFET

PartDrain to Source Voltage (Vdss)Package / CaseTechnologyVgs(th) (Max) @ IdConfiguration [custom]Configuration [custom]Input Capacitance (Ciss) (Max) @ VdsRds On (Max) @ Id, VgsSupplier Device PackageMounting TypeOperating Temperature [Min]Operating Temperature [Max]
Microchip Technology
TC8020K6-G
200 V
56-VFQFN Exposed Pad
MOSFET (Metal Oxide)
2.4 V
6
6
50 pF
8 Ohm
56-QFN (8x8)
Surface Mount
-55 °C
150 °C
Microchip Technology
TC8020K6-G
Microchip Technology
TC8020K6-G-M937
200 V
56-VFQFN Exposed Pad
MOSFET (Metal Oxide)
2.4 V
6
6
50 pF
8 Ohm
56-QFN (8x8)
Surface Mount
-55 °C
150 °C

Description

General part information

TC8020 Series

TC8020 consists of six pairs of high voltage, low threshold N- and P-channel MOSFETs in a 56-lead QFN package. All MOSFETs have integrated gate-to-source resistors and gate-to-source Zener diode clamps which are desired for high voltage pulser applications. The complementary, high-speed, high voltage, gate-clamped N- and P-channel MOSFET pairs utilize an advanced vertical DMOS structure and a well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input and output capacitance, and fast switching speeds are desired.