CD74HC109M

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Texas Instruments

HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET

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Search across all available documentation for this part.

DocumentsCD54HC109, CD74HC109, CD54HCT109, CD74HCT109 datasheet (Rev. E)

CD74HC109M

Active

Texas Instruments

HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET

Deep-Dive with AI

DocumentsCD54HC109, CD74HC109, CD54HCT109, CD74HCT109 datasheet (Rev. E)

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	CD74HC109M	74HC109 Series

Clock Frequency	60 MHz	60 MHz
Current - Output High, Low	5.2 mA, 5.2 mA	5.2 mA
Current - Quiescent (Iq)	4 çA	4 çA
Function	Reset, Set(Preset)	Reset, Set(Preset)
Input Capacitance	10 pF	3 - 10 pF
Max Propagation Delay @ V, Max CL	-	31 ns
Mounting Type	Surface Mount	Surface Mount, Through Hole
Number of Bits per Element	1	1
Number of Elements [custom]	2	2
Operating Temperature [Max]	125 °C	85 - 125 °C
Operating Temperature [Min]	-55 C	-55 - -40 °C
Output Type	Complementary	Complementary
Package / Case	16-SOIC	16-SOIC, 16-DIP, 16-SOIC (0.209", 5.30mm Width)
Package / Case	3.9 mm Width, 0.154 in	0.154 - 7.62 mm Width
Supplier Device Package	16-SOIC	16-SOIC, 16-PDIP, 16-SO
Trigger Type	Positive Edge	Positive Edge
Type	JK Type	JK Type
Voltage - Supply [Max]	6 V	6 V
Voltage - Supply [Min]	2 V	2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.43
		10	$ 1.27
		40	$ 1.21
		120	$ 0.99
		280	$ 0.93
		398	$ 0.75
		520	$ 0.82
Texas Instruments	TUBE	1	$ 1.23
		100	$ 0.83
		250	$ 0.64
		1000	$ 0.43

74HC109 Series

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Part	Function	Operating Temperature [Max]	Operating Temperature [Min]	Current - Quiescent (Iq)	Output Type	Input Capacitance	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Number of Elements [custom]	Supplier Device Package	Trigger Type	Clock Frequency	Number of Bits per Element	Package / Case	Package / Case	Current - Output High, Low	Max Propagation Delay @ V, Max CL
Texas Instruments SN74HC109DR Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	Reset, Set(Preset)	85 °C	-40 °C	4 çA	Complementary	3 pF	JK Type	2 V	6 V	Surface Mount	2	16-SOIC	Positive Edge	60 MHz	1	16-SOIC	0.154 in, 3.9 mm Width	5.2 mA, 5.2 mA
Texas Instruments SN74HC109N Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-DIP (0.300", 7.62mm)	Reset, Set(Preset)	85 °C	-40 °C	4 çA	Complementary	3 pF	JK Type	2 V	6 V	Through Hole	2	16-PDIP	Positive Edge	60 MHz	1	16-DIP	0.3 in, 7.62 mm	5.2 mA, 5.2 mA
Texas Instruments SN74HC109NSRE4 Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.209", 5.30mm Width)	Reset, Set(Preset)	85 °C	-40 °C	4 çA	Complementary	3 pF	JK Type	2 V	6 V	Surface Mount	2	16-SO	Positive Edge	60 MHz	1	16-SOIC (0.209", 5.30mm Width)		5.2 mA, 5.2 mA
Texas Instruments CD74HC109E The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.	Reset, Set(Preset)	125 °C	-55 C	4 çA	Complementary	10 pF	JK Type	2 V	6 V	Through Hole	2	16-PDIP	Positive Edge	60 MHz	1	16-DIP	0.3 in, 7.62 mm	5.2 mA, 5.2 mA	31 ns
Texas Instruments CD74HC109M The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.	Reset, Set(Preset)	125 °C	-55 C	4 çA	Complementary	10 pF	JK Type	2 V	6 V	Surface Mount	2	16-SOIC	Positive Edge	60 MHz	1	16-SOIC	0.154 in, 3.9 mm Width	5.2 mA, 5.2 mA
Texas Instruments SN74HC109NSR Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.209", 5.30mm Width)	Reset, Set(Preset)	85 °C	-40 °C	4 çA	Complementary	3 pF	JK Type	2 V	6 V	Surface Mount	2	16-SO	Positive Edge	60 MHz	1	16-SOIC (0.209", 5.30mm Width)		5.2 mA, 5.2 mA
Texas Instruments SN74HC109DT Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	Reset, Set(Preset)	85 °C	-40 °C	4 çA	Complementary	3 pF	JK Type	2 V	6 V	Surface Mount	2	16-SOIC	Positive Edge	60 MHz	1	16-SOIC	0.154 in, 3.9 mm Width	5.2 mA, 5.2 mA
Texas Instruments CD74HC109MG4 Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)	Reset, Set(Preset)	125 °C	-55 C	4 çA	Complementary	10 pF	JK Type	2 V	6 V	Surface Mount	2	16-SOIC	Positive Edge	60 MHz	1	16-SOIC	0.154 in, 3.9 mm Width	5.2 mA, 5.2 mA
Texas Instruments SN74HC109NG4 Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-DIP (0.300", 7.62mm)	Reset, Set(Preset)	85 °C	-40 °C	4 çA	Complementary	3 pF	JK Type	2 V	6 V	Through Hole	2	16-PDIP	Positive Edge	60 MHz	1	16-DIP	0.3 in, 7.62 mm	5.2 mA, 5.2 mA
Texas Instruments CD74HC109M96 The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.	Reset, Set(Preset)	125 °C	-55 C	4 çA	Complementary	10 pF	JK Type	2 V	6 V	Surface Mount	2	16-SOIC	Positive Edge	60 MHz	1	16-SOIC	0.154 in, 3.9 mm Width	5.2 mA, 5.2 mA

Description

General part information

74HC109 Series

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

Documents

Technical documentation and resources

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 datasheet (Rev. E)

Data sheet